How is FMV.X.H different from FCVT?
FMV copies the bit pattern; FCVT performs numeric conversion, can round, and can set exception flags.
FMV.X.H
RISC-V FMV.X.H Instruction Details
Instruction ManualR-typeBit-copy a half-precision floating-point encoding to an integer register.
Instruction Syntax
fmv.x.h rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
ZfhZfhminFloating-Point Bit Move
Instruction Behavior
Provided by Zfh or Zfhmin (each depends on F), FMV.X.H bit-copies the half-precision floating-point encoding in f[rs1] into x[rd], filling the upper XLEN-16 integer-register bits with copies of bit 15. This is a bit move, not a floating-point-to-integer numeric conversion; it does not round and sets no floating-point exception flags.
FMV.X.H Decode And Execute Animation
Shows the Zfh/Zfhmin-extension FMV.X.H bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
fmv.x.h
,
Execution Context
fmt=H (10)
FLEN>=32; H payload=16
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11100
funct5=to-x
10
fmt=H
00000
rs2=00000
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xE4058553
opcode
1010011 -> OP-FP
funct5/fmt
11100 + 10 -> funct7 1110010
rs2
00000 fixed for FMV.X.H
rd/rs1
a0(x10) / fa1(f11)
read bits
fa1(f11) = 0xC100
bit move
copy 16 bits; sign-extend bit15 -> 0xFFFFC100
write
a0(x10) = 0xFFFFC100; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xE4058553
syntax : fmv.x.h a0(x10), fa1(f11)
result : a0(x10) = 0xFFFFC100; fflags unchanged
Bit-Pattern Move View
FP source bits
0xC100
unchanged payload
0xC100
writeback
a0(x10) = 0xFFFFC100
FMV.X.H sign-extends half-precision bit 15 into the upper XLEN=32 bits; it does not perform numeric conversion.
This animation shows only Zfh/Zfhmin-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMV.X.H's core idea is bit-pattern movement. Use FCVT for numeric conversion and rounding; use FMV forms when preserving NaN payloads or inspecting raw encodings.
FMV.X.H is provided by Zfh or Zfhmin; each depends on F.
FMV instructions do not use an rm field.
A bit move does not canonicalize NaNs or change the input according to numeric value; FMV.X.H copies bit 15 into the upper integer-register bits.
Common Usage Scenarios
Floating-Point Bit Move
Understand this scenario with real code like «fmv.x.h x10, f0 # x10 = sign_extend(f0[15:0]) to XLEN bits».
Debugging Bit Patterns
Understand this scenario with real code like «fmv.x.h x10, f0 # x10 = sign_extend(f0[15:0]) to XLEN bits».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
This is a bit copy, not an FCVT numeric conversion.
It does not use rm and does not set fflags.
The integer destination holds the encoding bit pattern; the upper bits are sign-extended from bit 15, not a rounded integer value.
FAQ
Does FMV.X.H set fflags?
No. It is neither arithmetic nor numeric conversion.