Does FMV.D.X convert an integer value to double?
No. It writes the 64 integer-register bits unchanged as a double-precision encoding; use FCVT.D.L or related FCVT instructions for numeric conversion.
FMV.D.X
RISC-V FMV.D.X Instruction Details
Instruction ManualR-typeRV64 double-precision bit-pattern move from integer to FP register, with no numeric conversion.
Instruction Syntax
fmv.d.x rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
DFloating-Point Bit Move
Instruction Behavior
FMV.D.X moves the IEEE 754 double-precision 64-bit encoding between integer and floating-point registers. It does not modify transferred bits and preserves non-canonical NaN payloads; this form is defined only when XLEN>=64. When FLEN>64, the double-precision value written to the FP register is represented as a valid NaN-boxed narrower value.
FMV.D.X Decode And Execute Animation
Shows the D-extension FMV bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
fmv.d.x
,
Execution Context
fmt=D (01)
FLEN>=64
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11110
funct5=to-f
01
fmt=D
00000
rs2=00000
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xF2058553
opcode
1010011 -> OP-FP
funct5/fmt
11110 + 01 -> funct7 1111001
rs2
00000 fixed for FMV.D.X
rd/rs1
fa0(f10) / a1(x11)
read bits
a1(x11) = 0x400921FB54442D18
bit move
copy 64 bits -> 0x400921FB54442D18
write
fa0(f10) = 0x400921FB54442D18; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xF2058553
syntax : fmv.d.x fa0(f10), a1(x11)
result : fa0(f10) = 0x400921FB54442D18; fflags unchanged
Bit-Pattern Move View
integer low bits
0x400921FB54442D18
unchanged payload
0x400921FB54442D18
writeback
fa0(f10) = 0x400921FB54442D18
FMV.D.X is defined only when XLEN>=64 and writes the 64-bit double-precision encoding unchanged to the FP register; if FLEN is wider, it forms a valid NaN-boxed narrower value.
This animation shows only D-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMV.D.X is defined only when XLEN>=64 and writes 64 integer-register bits unchanged as a double-precision FP encoding. It is not integer-to-double numeric conversion; if FLEN is wider, the written value is represented using NaN-boxing.
In the D extension, this 64-bit move form requires XLEN>=64.
Transferred bits are unchanged, including non-canonical NaN payloads.
When FLEN>64, the double-precision value forms a valid NaN-boxed narrower value.
Common Usage Scenarios
double bit construction
Understand this scenario with real code like «fmv.d.x f0, x10 # f0 gets bits from x10 (NaN-boxed if FLEN>64)».
NaN payload preservation
Understand this scenario with real code like «fmv.d.x f0, x10 # f0 gets bits from x10 (NaN-boxed if FLEN>64)».
RV64 raw encoding debug
Understand this scenario with real code like «fmv.d.x f0, x10 # f0 gets bits from x10 (NaN-boxed if FLEN>64)».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
This is a bit-pattern move, not an integer/FP numeric conversion; use FCVT for conversion.
Defined only for XLEN>=64; RV32 has no FMV.D.X/FMV.X.D.
It sets no FP exception flags and does not canonicalize NaN payloads.
FAQ
Does FMV.D.X set fflags?
No. It performs no rounding, arithmetic, or numeric conversion.