Does FMV.W.X convert an integer to float?
No. It writes the low 32 source bits as a single-precision encoding into the FP register; use FCVT.S.W or related FCVT instructions for numeric conversion.
FMV.W.X
RISC-V FMV.W.X Instruction Details
Instruction ManualR-typeBit-copy low integer-register bits into a single-precision floating-point register.
Instruction Syntax
fmv.w.x rd, rs1
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
FFloating-Point Bit Move
Instruction Behavior
FMV.W.X bit-copies the low 32 bits of x[rs1] into f[rd] as a single-precision floating-point encoding; in a wider FLEN register the result is NaN-boxed. This is a bit move, not a numeric conversion.
FMV.W.X Decode And Execute Animation
Shows the F-extension FMV bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
fmv.w.x
,
Execution Context
fmt=S (00)
FLEN>=32
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11110
funct5=to-f
00
fmt=S
00000
rs2=00000
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xF0058553
opcode
1010011 -> OP-FP
funct5/fmt
11110 + 00 -> funct7 1111000
rs2
00000 fixed for FMV.W.X
rd/rs1
fa0(f10) / a1(x11)
read bits
a1(x11) = 0x40490FDB
bit move
copy low 32 bits -> 0x40490FDB; NaN-box in FP register
write
fa0(f10) = 0x40490FDB; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xF0058553
syntax : fmv.w.x fa0(f10), a1(x11)
result : fa0(f10) = 0x40490FDB; fflags unchanged
Bit-Pattern Move View
integer low bits
0x40490FDB
unchanged payload
0x40490FDB
writeback
fa0(f10) = 0x40490FDB
FMV.W.X takes only the low 32 bits of the integer source as the single-precision encoding; in wider FLEN registers it is stored using NaN-boxing.
This animation shows only F-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMV.W.X takes the low 32 bits from an integer register and places them unchanged in an FP register as a single-precision encoding. It does not convert an integer value to float; in wider FLEN registers the value is stored using NaN-boxing.
The OP-FP encoding uses fmt=S and fixed fields to select the FMV.W.X bit-move form.
Only the low 32 bits of x[rs1] are copied; rm is not used and fflags are not set.
When FLEN is greater than 32, the single-precision value is represented using NaN-boxing.
Common Usage Scenarios
FP bit construction
Understand this scenario with real code like «fmv.w.x f0, x10 # f0 gets bits from x10[31:0], NaN-boxed if FLEN>32».
NaN payload preservation
Understand this scenario with real code like «fmv.w.x f0, x10 # f0 gets bits from x10[31:0], NaN-boxed if FLEN>32».
raw encoding debugging
Understand this scenario with real code like «fmv.w.x f0, x10 # f0 gets bits from x10[31:0], NaN-boxed if FLEN>32».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
This is a bit copy, not an FCVT numeric conversion.
It does not use rm and does not set fflags.
The integer source provides only the low bits needed by the destination format.
FAQ
Does FMV.W.X set fflags?
No. It is not floating-point arithmetic or numeric conversion, and it performs no rounding.