Is FMVP.D.X an FCVT conversion?
No. It only copies the bit pattern and does not interpret and convert the numeric value.
FMVP.D.X
RISC-V FMVP.D.X Instruction Details
Instruction ManualR-typeOn RV32, combine two integer registers into one double-precision floating-point bit pattern.
Instruction Syntax
fmvp.d.x rd, rs1, rs2
Operand Breakdown
rd: FP f0–f31, including writable f0; rs1 and rs2: independent integer sources x0–x31 providing the low and high 32 bits.
x0 reads zero; equal sources require equal words. Sources need not be adjacent or even-numbered; no rm, rs3, or immediate.
ZfaDData Movement
Instruction Behavior
FMVP.D.X is a Zfa bit-move instruction for RV32+D that writes x[rs1] as the low 32 bits and x[rs2] as the high 32 bits of f[rd]. It is a bit copy, not an integer-to-floating numeric conversion, and it sets no floating-point exception flags.
FMVP.D.X Decode And Execute Animation
Shows the Zfa + D (RV32 only)-extension FMVP.D.X bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
rs2
fmvp.d.x
,
,
Execution Context
fmt=D (01)
FLEN>=64
Assumes RV32, D and Zfa with enabled FP state. An x0 word must be zero; equal integer sources require equal words. Wider FLEN destinations get upper ones.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
10110
funct5=to-f
01
fmt=D
01100
rs2 (high word)
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xB2C58553
opcode
1010011 -> OP-FP
funct5/fmt
10110 + 01 -> funct7 1011001
rs2
01100 -> a2(x12) (high word)
rd/rs1
fa0(f10) / a1(x11) (low) / a2(x12) (high)
read bits
Source registers not read yet
bit move
Awaiting Execute
write
Not written yet
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xB2C58553
syntax : fmvp.d.x fa0(f10), a1(x11), a2(x12)
result : Not written yet
Bit-Pattern Move View
a1(x11) low 32
0x54442D18
a2(x12) high 32
0x400921FB
assembled double bits
Awaiting Execute
writeback
Not written yet
FMVP.D.X is defined only for RV32+D+Zfa: x[rs1] supplies bits 31:0 and x[rs2] supplies bits 63:32, assembled unchanged into f[rd] as a double-precision bit pattern.
This animation shows only Zfa + D (RV32 only)-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMVP.D.X fills the RV32 path for moving a 64-bit double encoding through 32-bit integer registers. The key points are bit order and that it is not numeric conversion.
RV32 Zfa+D only, with enabled FP state. rd selects f0–f31; rs1 and rs2 independently select integer registers x0–x31.
32-bit OP-FP R-type: funct7=1011001, rs2[24:20], rs1[19:15], funct3=000, rd[11:7], opcode=1010011. There is no rm or immediate.
f[rd][63:0] = (x[rs2][31:0] << 32) | x[rs1][31:0]: rs1 is the low word and rs2 the high word. Equal source registers provide one initial value; x0 provides zero.
This bit copy performs no FCVT numeric conversion, rounding or NaN-payload canonicalization, and sets no FP exception flags. When FLEN>64, upper result bits are ones for a valid NaN box.
Common Usage Scenarios
Floating-Point Bit Move
Assume RV32 Zfa+D, enabled FP state, x11=0x89ABCDEF and x12=0x01234567: the example writes f10[63:0]=0x0123456789ABCDEF with unchanged fflags. For FLEN=128 the upper 64 bits are all ones; no numeric FP interpretation is performed.
RV32 Double Data Movement
Assume RV32 Zfa+D, enabled FP state, x11=0x89ABCDEF and x12=0x01234567: the example writes f10[63:0]=0x0123456789ABCDEF with unchanged fflags. For FLEN=128 the upper 64 bits are all ones; no numeric FP interpretation is performed.
Pre-Use Checklist
Syntax Check
- rd: FP f0–f31, including writable f0; rs1 and rs2: independent integer sources x0–x31 providing the low and high 32 bits.
- x0 reads zero; equal sources require equal words. Sources need not be adjacent or even-numbered; no rm, rs3, or immediate.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
Defined only for RV32 with both Zfa and D; it is not an RV64 instruction. rs1 and rs2 are independently encoded, with no adjacency or even-register requirement.
This is a bit copy, not an FCVT numeric conversion.
It sets no floating-point exception flags.
FAQ
Why does FMVP.D.X emphasize RV32?
It is defined only for RV32 Zfa+D, combining two independently selected 32-bit integer sources into a 64-bit double-precision bit pattern; it is not an RV64 instruction.