Is FMVP.D.X an FCVT conversion?
No. It only copies the bit pattern and does not interpret and convert the numeric value.
FMVP.D.X
RISC-V FMVP.D.X Instruction Details
Instruction ManualR-typeOn RV32, combine two integer registers into one double-precision floating-point bit pattern.
Instruction Syntax
fmvp.d.x rd, rs1, rs2
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
ZfaDData Movement
Instruction Behavior
FMVP.D.X is a Zfa bit-move instruction for RV32+D that writes x[rs1] as the low 32 bits and x[rs2] as the high 32 bits of f[rd]. It is a bit copy, not an integer-to-floating numeric conversion, and it sets no floating-point exception flags.
FMVP.D.X Decode And Execute Animation
Shows the Zfa + D (RV32 only)-extension FMVP.D.X bit-pattern move: decode OP-FP fields, read the source bit pattern, then write the destination without numeric conversion.
rd
rs1
rs2
fmvp.d.x
,
,
Execution Context
fmt=D (01)
FLEN>=64
31..27
26..25
24..20
19..15
14..12
11..7
6..0
10110
funct5=to-f
01
fmt=D
01100
rs2 (high word)
01011
rs1
000
funct3=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xB2C58553
opcode
1010011 -> OP-FP
funct5/fmt
10110 + 01 -> funct7 1011001
rs2
01100 -> a2(x12) (high word)
rd/rs1
fa0(f10) / a1(x11) (low) / a2(x12) (high)
read bits
a1(x11)[31:0]=0x54442D18; a2(x12)[31:0]=0x400921FB
bit move
concatenate rs2[31:0]:rs1[31:0] -> 0x400921FB54442D18
write
fa0(f10) = 0x400921FB54442D18; fflags unchanged
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FMV bit moves use opcode 1010011.
encoding: 0xB2C58553
syntax : fmvp.d.x fa0(f10), a1(x11), a2(x12)
result : fa0(f10) = 0x400921FB54442D18; fflags unchanged
Bit-Pattern Move View
a1(x11) low 32
0x54442D18
a2(x12) high 32
0x400921FB
assembled double bits
0x400921FB54442D18
writeback
fa0(f10) = 0x400921FB54442D18
FMVP.D.X is defined only for RV32+D+Zfa: x[rs1] supplies bits 31:0 and x[rs2] supplies bits 63:32, assembled unchanged into f[rd] as a double-precision bit pattern.
This animation shows only Zfa + D (RV32 only)-extension FMV ISA-visible encoding and bit-pattern movement; it does not model FPU pipelines, numeric FP interpretation, exception handling, or microarchitecture.
Quick Understanding & Search Notes
FMVP.D.X fills the RV32 path for moving a 64-bit double encoding through 32-bit integer registers. The key points are bit order and that it is not numeric conversion.
FMVH.X.D takes the high 32 bits; FMVP.D.X uses rs1 for the low 32 bits and rs2 for the high 32 bits.
These instructions do not use rm and do not alter NaN payloads.
Common Usage Scenarios
Floating-Point Bit Move
Understand this scenario with real code like «fmvp.d.x f10, x11, x12 ; f10 = {x12, x11} (RV32 double)».
RV32 Double Data Movement
Understand this scenario with real code like «fmvp.d.x f10, x11, x12 ; f10 = {x12, x11} (RV32 double)».
Pre-Use Checklist
Syntax Check
- rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
- FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
Semantic Check
- Confirm this is bit copying, not floating/integer numeric conversion.
- Confirm destination direction, sign-extension, or NaN-boxing rules for this FMV variant.
Pitfalls / Common Confusions
Used for RV32+D double-precision bit movement; RV64 normally uses FMV.X.D/FMV.D.X.
This is a bit copy, not an FCVT numeric conversion.
It sets no floating-point exception flags.
FAQ
Why does FMVP.D.X emphasize RV32?
Because RV32 integer registers are only 32 bits wide, so a 64-bit double encoding must be moved in a pair.