Is FMVP.D.X an FCVT conversion?
No. It only copies the bit pattern and does not interpret and convert the numeric value.
FMVP.D.X
RISC-V FMVP.D.X Instruction Details
Instruction ManualR-typeOn RV32, combine two integer registers into one double-precision floating-point bit pattern.
Instruction Syntax
fmvp.d.x rd, rs1, rs2
Operand Breakdown
rd/rs fields denote integer or floating-point registers depending on the direction of this instruction.
FMV forms copy bit patterns; they are not FCVT numeric conversions and do not use rm.
ZfaDData Movement
Instruction Behavior
FMVP.D.X is a Zfa bit-move instruction for RV32+D that writes x[rs1] as the low 32 bits and x[rs2] as the high 32 bits of f[rd]. It is a bit copy, not an integer-to-floating numeric conversion, and it sets no floating-point exception flags.
Quick Understanding & Search Notes
FMVP.D.X fills the RV32 path for moving a 64-bit double encoding through 32-bit integer registers. The key points are bit order and that it is not numeric conversion.
FMVH.X.D takes the high 32 bits; FMVP.D.X uses rs1 for the low 32 bits and rs2 for the high 32 bits.
These instructions do not use rm and do not alter NaN payloads.
Common Usage Scenarios
Floating-Point Bit Move
Understand this scenario with real code like «fmvp.d.x f10, x11, x12 ; f10 = {x12, x11} (RV32 double)».
RV32 Double Data Movement
Understand this scenario with real code like «fmvp.d.x f10, x11, x12 ; f10 = {x12, x11} (RV32 double)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Used for RV32+D double-precision bit movement; RV64 normally uses FMV.X.D/FMV.D.X.
This is a bit copy, not an FCVT numeric conversion.
It sets no floating-point exception flags.
FAQ
Why does FMVP.D.X emphasize RV32?
Because RV32 integer registers are only 32 bits wide, so a 64-bit double encoding must be moved in a pair.