Can LB.AQ use offset(rs1)?
No. The official syntax is lb.aq rd, (rs1), with no offset immediate; the address comes directly from rs1.
LB.AQ
RISC-V LB.AQ Instruction Details
Instruction ManualAMOZalasr atomic load of 1 byte with acquire-RCsc ordering.
Instruction Syntax
lb.aq rd, (rs1)
Operand Breakdown
Destination rd: receives the sign-extended load result; if rd=x0, the writeback is discarded.
Address register rs1: directly supplies the memory address; Zalasr syntax has no offset immediate.
Encoding field rs2 is fixed to 00000; aq must be 1, and aq/rl only annotate ordering.
ZalasrCache & Synchronization
Instruction Behavior
LB.AQ is a 1-byte ordered atomic load in the Zalasr standalone load-acquire/store-release family. It atomically reads 8 bits from the address in x[rs1], sign-extends from that width, and writes x[rd]; the syntax has no offset field. Every byte address is naturally aligned for this 1-byte access; the example assumes access is permitted and completes successfully.
LB.AQ Zalasr Decode And Execute Animation
Shows the Zalasr standalone load-acquire AMO encoding, no-offset address syntax, 8-bit data transfer, and aq/rl ordering annotation.
rd
rs1
lb.aq,()
Execution Context
Ordering Annotation
aq=1, rl=0 (acquire)
A 1-byte access is naturally aligned at every byte address. Assume successful permitted fetch/access and implemented Zalasr. This illustrates the load and ordering annotation, without a concurrent schedule. Address samples are nonnegative safe integers and also fit 32 bits on RV32; this is a demo input limit. rd=x0 still performs the load and its side effects, discarding only the result.
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00110
funct5
1
aq
0
rl
00000
rs2=00000
01010
rs1
000
funct3
00101
rd
0101111
opcode
Zalasr Data Path
instruction
0x340502AF
opcode
0101111 -> AMO major opcode
funct5
00110 -> LB.AQ
aq / rl
1/0 -> acquire
operands
rd=t0(x5), rs1=a0(x10)
address
a0(x10) -> 0x00001000 (no offset); naturally aligned
memory read
mem[0x00001000] -> 0xF2
execute
sign_extend(0xF2, 8) -> 0xFFFFFFF2
writeback
t0(x5) = 0xFFFFFFF2
8-bit Transfer View
7
6
5
4
3
2
1
0
1
1
1
1
0
0
1
0
memory 8
-
-
-
-
-
-
-
-
LB.AQ loads 8 bits from memory and sign-extends from that width to XLEN before writing rd.
This animation shows ISA-visible Zalasr atomic load/store behavior and aq/rl ordering annotations; it does not model LR/SC reservations, AMO read-modify-write old-value return, caches, buses, or pipeline timing.
Quick Understanding & Search Notes
LB.AQ uses rs1 directly as the address, atomically reads 1 byte, and sign-extends into rd; aq/rl bits provide ordering annotations and do not change the loaded data.
The syntax is lb.aq rd, (rs1), with no offset field; the address comes from x[rs1].
funct5=00110 selects the Zalasr load-acquire class, funct3=000 selects the LB.AQ access width, the AMO major opcode is 0101111, and the aq bit must be 1 for Zalasr loads.
The 8-bit loaded value is sign-extended from the source width to XLEN.
LB.AQ has aq=1 and rl=0: it has acquire-RCsc, not release-RCsc, annotation. aq/rl do not change the load, sign extension, or rd=x0 architectural behavior.
The rs2 field is fixed to 00000. rd=x0 discards the loaded value but does not suppress the memory access, exceptions, or other side effects.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lb.aq x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «lb.aq x5, (x6)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is AMO.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The syntax has no offset immediate; the address comes directly from rs1.
The load result is sign-extended from the 8-bit source width to XLEN; Zalasr has no unsigned load form.
Zalasr load encodings without aq set are RESERVED.
Zalasr is a single ordered atomic load/store instruction, not an LR/SC reservation protocol or an AMO read-modify-write old-value return.
FAQ
Is LB.AQ an LR/SC or AMO read-modify-write operation?
No. These Zalasr instructions are single ordered atomic load/store operations; the animation does not show reservations or old-value return.
Do aq/rl bits change the data result?
No. aq/rl are ordering annotations; the loaded value is still sign-extended from the source width into rd.