LD.AQRL

RISC-V LD.AQRL Instruction Details

Instruction ManualAMO

Zalasr atomic load of 8 bytes with acquire+release-RCsc ordering (RV64-only).

Instruction Syntax

ld.aqrl rd, (rs1)

rd: receives all 64 loaded bits, on RV64 only; rd=x0 discards only writeback while retaining load exceptions and side effects.

rs1: supplies the pre-execution address directly, with no offset immediate. rs1=x0 gives address zero; rd=rs1 still uses the address before writeback.

The rs2 field is fixed to 00000 and is not an assembly operand. aq=1, while .aq or .aqrl selects rl; both bits specify ordering annotations only.

ZalasrCache & Synchronization

Related Search Terms

ld.aqrl instruction RISC-V ld.aqrl ld.aqrl syntax ld.aqrl encoding Zalasr atomic load acquire-release instruction ld.aqrl alignment

Instruction Behavior

LD.AQRL is an RV64-only atomic load in Zalasr 1.0. On a successful access, it atomically reads 8 bytes at x[rs1] and writes all 64 bits to x[rd]; the source width equals XLEN, so no widening is needed. There is no offset field. Use 8-byte alignment unless all accessed bytes lie in one misaligned atomicity-granule PMA.

LD.AQRL Zalasr Decode And Execute Animation

Shows the Zalasr standalone load-acquire AMO encoding, no-offset address syntax, 64-bit data transfer, and aq/rl ordering annotation.

rs1

ld.aqrl

)

Execution Context

XLENmemory addressmemory 64-bit valueWithin one misaligned atomicity-granule PMA

Ordering Annotation

aq=1, rl=1 (acquire+release)

For an address not naturally aligned to 8 bytes, the checkbox only asserts that all accessed bytes lie in one misaligned atomicity-granule PMA. Without that assertion, the model shows the permitted address-misaligned or access-fault branch; it does not determine a platform's PMA.

Assume implemented Zalasr and successful permitted fetch/data access except for the shown alignment exception. Address samples are nonnegative safe integers (at most 2^53−1), also fitting 32 bits on RV32; this is a demo input limit. rd=x0 still performs the load and its side effects, discarding only the result; rd=rs1 uses the address before writeback.

31..27

24..20

19..15

14..12

11..7

6..0

00110

funct5

00000

rs2=00000

01010

rs1

011

funct3

00101

0101111

opcode

Zalasr Data Path

instruction

0x360532AF

opcode

0101111 -> AMO major opcode

funct5

00110 -> LD.AQRL

aq / rl

1/1 -> acquire+release

operands

rd=t0(x5), rs1=a0(x10)

address

a0(x10) -> 0x0000000000001000 (no offset); naturally aligned

memory read

mem[0x0000000000001000] -> 0x8000000000000002

execute

copy64(0x8000000000000002, 64) -> 0x8000000000000002

writeback

t0(x5) = 0x8000000000000002

64-bit Transfer View

LD.AQRL loads all 64 bits into rd; the width equals XLEN, so no additional sign bits are needed.

This animation shows ISA-visible Zalasr atomic load/store behavior and aq/rl ordering annotations; it does not model LR/SC reservations, AMO read-modify-write old-value return, caches, buses, or pipeline timing.

Quick Understanding & Search Notes

LD.AQRL uses x[rs1] as the address, atomically reads 8 bytes, and writes all 64 bits into rd. It is RV64-only; aq/rl specify ordering annotations.

The syntax is ld.aqrl rd, (rs1), with no offset field; the address comes from x[rs1].

32-bit AMO encoding: funct5[31:27]=00110, aq[26]=1, rl[25]=1, rs2[24:20]=00000, rs1[19:15], funct3[14:12]=011, rd[11:7], opcode[6:0]=0101111.

RV64-only: the load width and XLEN are both 64 bits, so no additional sign bits are needed.

LD.AQRL has aq=1 and rl=1: it has both acquire-RCsc and release-RCsc annotations. aq/rl do not change the load, sign extension, or rd=x0 architectural behavior.

Requires implemented Zalasr 1.0; this form is RV64-only. The address must be naturally 8-byte aligned, otherwise an address-misaligned or access-fault exception is generated. If all accessed bytes lie in one misaligned atomicity-granule PMA, no address-alignment exception is raised and atomicity is retained.

rd=x0 discards only writeback; the load must still cause exceptions and other side effects. rs1=x0 means address zero. When rd=rs1, the address uses the register value before writeback.

Example: assume implemented Zalasr and successful permitted fetch/data access. On RV64, with x6=0x1000 and the 64-bit memory value 0x8000000000000002, ld.aqrl x5, (x6) gives x5=0x8000000000000002; memory is unchanged.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, §§17.1–17.2

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «ld.aqrl x5, (x6)».

Concurrency & Multi-core

Understand this scenario with real code like «ld.aqrl x5, (x6)».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is AMO.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The syntax has no offset immediate; the address comes directly from rs1.

RV64-only: all 64 loaded bits are written to rd unchanged; there is no separate unsigned form.

Zalasr load encodings without aq set are RESERVED.

Zalasr is a standalone ordered atomic load; it does not use LR/SC reservations or perform AMO read-modify-write.

FAQ

Can LD.AQRL use offset(rs1)?

No. The syntax is ld.aqrl rd, (rs1); rs1 supplies the address, with no offset field.

Is LD.AQRL an LR/SC or AMO read-modify-write operation?

No. It is an atomic load, with neither a reservation nor a read-modify-write.

Do aq/rl bits change the data result?

No. aq/rl are ordering annotations; the complete 64-bit LD value is unchanged, with only writeback discarded for rd=x0.