Can LH.AQRL use offset(rs1)?
No. The official syntax is lh.aqrl rd, (rs1), with no offset immediate; the address comes directly from rs1.
LH.AQRL
RISC-V LH.AQRL Instruction Details
Instruction ManualR-typeZalasr atomic load of 2 bytes with acquire+release-RCsc ordering.
Instruction Syntax
lh.aqrl rd, (rs1)
Operand Breakdown
Destination rd: receives the sign-extended load result; if rd=x0, the writeback is discarded.
Address register rs1: directly supplies the memory address; Zalasr syntax has no offset immediate.
Encoding field rs2 is fixed to 00000; aq must be 1, and aq/rl only annotate ordering.
ZalasrCache & Synchronization
Instruction Behavior
LH.AQRL is a 2-byte ordered atomic load in the Zalasr standalone load-acquire/store-release family. It atomically reads 16 bits from the address in x[rs1], sign-extends from that width, and writes x[rd]; the syntax has no offset field. The address is naturally aligned to the access width by default unless relaxed by the misaligned atomicity granule PMA.
LH.AQRL Zalasr Decode And Execute Animation
Shows the Zalasr standalone load-acquire AMO encoding, no-offset address syntax, 16-bit data transfer, and aq/rl ordering annotation.
rd
rs1
lh.aqrl,()
Ordering Annotation
aq=1, rl=1 (acquire+release)
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00110
funct5
1
aq
1
rl
00000
rs2=00000
01010
rs1
001
funct3
00101
rd
0101111
opcode
Zalasr Data Path
instruction
0x360512AF
opcode
0101111 -> AMO major opcode
funct5
00110 -> LH.AQRL
aq / rl
1/1 -> acquire+release
operands
rd=t0(x5), rs1=a0(x10)
address
a0(x10) -> 0x00001000 (no offset)
memory read
mem[0x00001000] -> 0xFFF2
execute
sign_extend(0xFFF2, 16) -> 0xFFFFFFF2
writeback
t0(x5) = 0xFFFFFFF2
16-bit Transfer View
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
memory 16
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LH.AQRL loads 16 bits from memory and sign-extends from that width to XLEN before writing rd.
This animation shows ISA-visible Zalasr atomic load/store behavior and aq/rl ordering annotations; it does not model LR/SC reservations, AMO read-modify-write old-value return, caches, buses, or pipeline timing.
Quick Understanding & Search Notes
LH.AQRL uses rs1 directly as the address, atomically reads 2 bytes, and sign-extends into rd; aq/rl bits provide ordering annotations and do not change the loaded data.
The syntax is lh.aqrl rd, (rs1), with no offset field; the address comes from x[rs1].
funct5=00110 selects the Zalasr load-acquire class, funct3=001 selects the LH.AQRL access width, the AMO major opcode is 0101111, and the aq bit must be 1 for Zalasr loads.
The 16-bit loaded value is sign-extended from the source width to XLEN.
aq/rl describe memory ordering only; they do not change the load, sign extension, or rd=x0 architectural behavior.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lh.aqrl x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «lh.aqrl x5, (x6)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The syntax has no offset immediate; the address comes directly from rs1.
The load result is sign-extended from the 16-bit source width to XLEN; Zalasr has no unsigned load form.
Zalasr load encodings without aq set are RESERVED.
Zalasr is a single ordered atomic load/store instruction, not an LR/SC reservation protocol or an AMO read-modify-write old-value return.
FAQ
Is LH.AQRL an LR/SC or AMO read-modify-write operation?
No. These Zalasr instructions are single ordered atomic load/store operations; the animation does not show reservations or old-value return.
Do aq/rl bits change the data result?
No. aq/rl are ordering annotations; the loaded value is still sign-extended from the source width into rd.