Does ROLW access memory?
No. This instruction reads its integer source registers and writes the computed result to rd; it performs no data-memory load or store.
ROLW
RISC-V ROLW Instruction Details
Instruction ManualR-typeRotate left word by register (RV64)
Instruction Syntax
rolw rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: integer registers x0–x31; no immediate or rs3 operand.
32-bit OP-32: opcode=0111011, funct7=0110000, funct3=001; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV64 only; requires enabled Zbb or Zbkb; B includes Zbb.
Rotate within 32 bits by rs2[4:0], then sign-extend result bit31 to 64 bits.
x0 is always zero and discards writes; rd may overlap a source, using source values before writeback. Only integer registers are operated on, with no data-memory access.
BZbbZbkbBit Manipulation
Instruction Behavior
RV64 only: rotate rs1[31:0] left by rs2[4:0], then sign-extend bit 31 to 64 bits. Available with Zbb or Zbkb.
ROLW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
rolw
,
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
a0(x10)
0x0000000000001000
t1(x6)
0x0000000000000014
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
00110
rs2
01010
rs1
001
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x606512BB
opcode
0111011 -> OP-32
funct3
001 -> ROLW
funct7
0110000 -> ROLW selector
rd / rs1[31:0] / rs2[4:0]
t0(x5) / a0(x10)[31:0]=0x00001000 / t1(x6)[4:0]=20
rotate left
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x606512BB
syntax : rolw t0(x5), a0(x10), t1(x6)
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
RV64 only: rotate rs1[31:0] left by rs2[4:0], then sign-extend bit 31 of the 32-bit result to 64 bits.
The W-suffixed form operates only on the low 32 bits of rs1 and uses a 5-bit amount.
The 32-bit result is sign-extended from bit 31 to XLEN; it is not an ordinary 64-bit rotate.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «rolw x10, x11, x12 ; x10 = sign_ext(rotl(x11[31:0], x12[4:0]))».
Crypto & Security
Understand this scenario with real code like «rolw x10, x11, x12 ; x10 = sign_ext(rotl(x11[31:0], x12[4:0]))».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: integer registers x0–x31; no immediate or rs3 operand.
- 32-bit OP-32: opcode=0111011, funct7=0110000, funct3=001; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV64 only; requires enabled Zbb or Zbkb; B includes Zbb.
- Rotate within 32 bits by rs2[4:0], then sign-extend result bit31 to 64 bits.
- x0 is always zero and discards writes; rd may overlap a source, using source values before writeback. Only integer registers are operated on, with no data-memory access.
Pitfalls / Common Confusions
RV64 only
Operates on lower 32 bits
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
The rotate amount comes from rs2[4:0]; this is a register field, not an immediate encoding.
FAQ
What is the result width of ROLW?
ROLW first produces a 32-bit rotated result, then sign-extends bit 31 to the 64-bit value written to rd.