Does ROLW access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
ROLW
RISC-V ROLW Instruction Details
Instruction ManualR-typeRotate left word by register (RV64)
Instruction Syntax
rolw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbZbkbBit Manipulation
Instruction Behavior
Rotates lower 32 bits of rs1 left by rs2[4:0], result sign-extended to XLEN. Part of Zbb and Zbkb.
ROLW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
rolw
,
,
Execution Context
a0(x10)
0x0000000000001000
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
00110
rs2
01010
rs1
001
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x606512BB
opcode
0111011 -> OP-32
funct3
001 -> ROLW
funct7
0110000 -> ROLW selector
rd / rs1[31:0] / rs2[4:0]
t0(x5) / a0(x10)[31:0]=0x00001000 / t1(x6)[4:0]=20
rotate left
rotl32(0x00001000, 20)=0x00000001; sign_extend(bit 31) -> 0x0000000000000001
x5
t0(x5) = 0x0000000000000001
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x606512BB
syntax : rolw t0(x5), a0(x10), t1(x6)
result : t0(x5) = 0x0000000000000001
Architectural Result
t0(x5) = 0x0000000000000001
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
ROLW is a B/Zbb instruction for rotate-left word and sign-extend. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
The W-suffixed form operates only on the low 32 bits of rs1 and uses a 5-bit amount.
The 32-bit result is sign-extended from bit 31 to XLEN; it is not an ordinary 64-bit rotate.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «rolw x10, x11, x12 ; x10 = sign_ext(rotl(x11[31:0], x12[4:0]))».
Crypto & Security
Understand this scenario with real code like «rolw x10, x11, x12 ; x10 = sign_ext(rotl(x11[31:0], x12[4:0]))».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
RV64 only
Operates on lower 32 bits
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
The rotate amount comes from rs2[4:0]; this is a register field, not an immediate encoding.
FAQ
What is the result width of ROLW?
ROLW first produces a 32-bit rotated result, then sign-extends bit 31 to the 64-bit value written to rd.