Does ROL access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
ROL
RISC-V ROL Instruction Details
Instruction ManualR-typeRotate left by register
Instruction Syntax
rol rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbBit ManipulationInteger Operation
Related Search Terms
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
ROL uses opcode 0110011 (0x33), funct3 001, funct7 0110000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 001 (0x1)
funct7: 0110000 (0x30)
Instruction Behavior
Rotates rs1 left by the lower log2(XLEN) bits of rs2. Part of Zbb and Zbkb. Replaces neg/sll/srl/or four-instruction sequence.
Quick Understanding & Search Notes
ROL is a B/Zbb instruction for XLEN-wide rotate left. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
The rotate amount comes from the low log2(XLEN) bits of rs2.
Rotates wrap shifted-out bits around to the other end; they are not logical shifts.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «rol x10, x11, x12 ; x10 = rotl(x11, x12 & (XLEN-1))».
Crypto & Security
Understand this scenario with real code like «rol x10, x11, x12 ; x10 = rotl(x11, x12 & (XLEN-1))».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Shift amount is modulo XLEN
Differs from logical shift: bits wrap around
FAQ
What is the result width of ROL?
Except that W-suffixed forms produce a 32-bit result then sign-extend and .uw forms first extract a 32-bit unsigned operand, the result is written to rd at XLEN width.