Does ROL access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
ROL
RISC-V ROL Instruction Details
Instruction ManualR-typeRotate left by register
Instruction Syntax
rol rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbZbkbBit ManipulationInteger Operation
Related Search Terms
Instruction Behavior
Rotates rs1 left by the lower log2(XLEN) bits of rs2. Part of Zbb and Zbkb. Replaces neg/sll/srl/or four-instruction sequence.
ROL Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
rol
,
,
Execution Context
a0(x10)
0x00001000
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
00110
rs2
01010
rs1
001
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x606512B3
opcode
0110011 -> OP
funct3
001 -> ROL
funct7
0110000 -> ROL selector
rd / rs1 / rs2
t0(x5) / a0(x10)=0x00001000 / t1(x6)[4:0]=20
rotate left
rol(0x00001000, 20) -> 0x00000001
x5
t0(x5) = 0x00000001
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x606512B3
syntax : rol t0(x5), a0(x10), t1(x6)
result : t0(x5) = 0x00000001
Architectural Result
t0(x5) = 0x00000001
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
ROL is a B/Zbb instruction for XLEN-wide rotate left. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
The rotate amount comes from the low log2(XLEN) bits of rs2.
Rotates wrap shifted-out bits around to the other end; they are not logical shifts.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «rol x10, x11, x12 ; x10 = rotl(x11, x12 & (XLEN-1))».
Crypto & Security
Understand this scenario with real code like «rol x10, x11, x12 ; x10 = rotl(x11, x12 & (XLEN-1))».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Shift amount is modulo XLEN
Differs from logical shift: bits wrap around
FAQ
What is the result width of ROL?
ROL rotates at the complete XLEN width and writes an equally wide result to rd: rs2[4:0] in RV32 and rs2[5:0] in RV64.