Does RORI access memory?
It does not access data memory; it reads integer source registers and writes the computed result to rd.
RORI
RISC-V RORI Instruction Details
Instruction ManualI-typeRotate right by immediate
Instruction Syntax
rori rd, rs1, shamt
Operand Breakdown
rd, rs1: integer registers x0–x31; shamt is 0–31 on RV32 or 0–63 on RV64, without sign extension.
32-bit OP-IMM: opcode=0010011, funct3=101; RV32 fixes imm[11:5]=0110000, with shamt[5]=1 encodings reserved; RV64 fixes imm[11:6]=011000, with bit25 as shamt[5].
RV32/RV64; requires enabled Zbb or Zbkb; B includes Zbb.
Rotate right within XLEN bits, wrapping low bits to the high end; a zero amount preserves the source bit pattern.
x0 is always zero and discards writes; rd may overlap a source, using values before writeback. Only integer registers are operated on, with no data-memory access.
BZbbZbkbBit ManipulationInteger Operation
Instruction Behavior
Rotates rs1 right by shamt (immediate). Range 0-31 (RV32) or 0-63 (RV64). Part of Zbb and Zbkb.
RORI Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
rori
,
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0110000
fixed imm[11:5]
01000
shamt[4:0]
00110
rs1
101
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x60835293
opcode
0010011 -> OP-IMM
funct3
101 -> RORI
imm[11:5]
imm[11:5]=0110000 fixed
rd / rs1
t0(x5) / t1(x6)
imm[11:5] + shamt[4:0]
imm[11:5]=0110000 fixed; shamt[4:0]=01000
rotate right
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x60835293
syntax : rori t0(x5), t1(x6), 8
Result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
RORI rotates rs1 right by shamt and writes an XLEN-wide result to rd. RV32 permits only a 5-bit shift amount; RV64 uses 6 bits.
The immediate uses a 5-bit amount on RV32 and a 6-bit amount on RV64.
On RV32, encodings with shamt[5]=1 are reserved; on RV64, bit 25 is shamt[5].
Common Usage Scenarios
Rotate right
RV32 with Zbb (or Zbkb), x11=0x12345678: rori x10, x11, 16 writes x10=0x56781234.
Pre-Use Checklist
Syntax Check
- rd, rs1: integer registers x0–x31; shamt is 0–31 on RV32 or 0–63 on RV64, without sign extension.
- 32-bit OP-IMM: opcode=0010011, funct3=101; RV32 fixes imm[11:5]=0110000, with shamt[5]=1 encodings reserved; RV64 fixes imm[11:6]=011000, with bit25 as shamt[5].
Semantic Check
- RV32/RV64; requires enabled Zbb or Zbkb; B includes Zbb.
- Rotate right within XLEN bits, wrapping low bits to the high end; a zero amount preserves the source bit pattern.
- x0 is always zero and discards writes; rd may overlap a source, using values before writeback. Only integer registers are operated on, with no data-memory access.
Pitfalls / Common Confusions
shamt limited to 31 on RV32
FAQ
What is the result width of RORI?
RORI writes the XLEN-wide rotated result to rd; it neither first truncates to 32 bits nor sign-extends a word result.