Does RORI access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
RORI
RISC-V RORI Instruction Details
Instruction ManualI-typeRotate right by immediate
Instruction Syntax
rori rd, rs1, shamt
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
BZbbBit ManipulationInteger Operation
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
RORI uses opcode 0010011 (0x13), funct3 101, funct7 0110000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0010011 (0x13)
funct3: 101 (0x5)
funct7: 0110000 (0x30)
Instruction Behavior
Rotates rs1 right by shamt (immediate). Range 0-31 (RV32) or 0-63 (RV64). Part of Zbb and Zbkb.
Quick Understanding & Search Notes
RORI is a B/Zbb instruction for rotate right by immediate. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
The immediate uses a 5-bit amount on RV32 and a 6-bit amount on RV64.
There is no ROLI mnemonic; a left rotate can be expressed with the equivalent right-rotate immediate.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «rori x10, x11, 16 ; x10 = rotr(x11, 16)».
Shift & Rotate
Understand this scenario with real code like «rori x10, x11, 16 ; x10 = rotr(x11, 16)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
shamt limited to 31 on RV32
FAQ
What is the result width of RORI?
Except that W-suffixed forms produce a 32-bit result then sign-extend and .uw forms first extract a 32-bit unsigned operand, the result is written to rd at XLEN width.