Does ROR access memory?
No. This instruction reads its integer source registers and writes the computed result to rd; it performs no data-memory load or store.
ROR
RISC-V ROR Instruction Details
Instruction ManualR-typeRotate right by register
Instruction Syntax
ror rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: integer registers x0–x31; no immediate or rs3 operand.
32-bit OP: opcode=0110011, funct7=0110000, funct3=101; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV32/RV64; requires enabled Zbb or Zbkb; B includes Zbb.
Rotate right within XLEN bits by rs2[4:0] in RV32 or rs2[5:0] in RV64; a zero amount preserves the source bit pattern.
x0 is always zero and discards writes; rd may overlap a source, using source values before writeback. Only integer registers are operated on, with no data-memory access.
BZbbZbkbBit ManipulationInteger Operation
Related Search Terms
Instruction Behavior
Rotates rs1 right by the lower log2(XLEN) bits of rs2. Part of Zbb and Zbkb.
ROR Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
ror
,
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
a0(x10)
0x00001000
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
00110
rs2
01010
rs1
101
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x606552B3
opcode
0110011 -> OP
funct3
101 -> ROR
funct7
0110000 -> ROR selector
rd / rs1 / rs2
t0(x5) / a0(x10)=0x00001000 / t1(x6)[4:0]=20
rotate right
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x606552B3
syntax : ror t0(x5), a0(x10), t1(x6)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Rotate rs1 right by rs2[4:0] in RV32 or rs2[5:0] in RV64; bits leaving the low end wrap to the high end.
The rotate amount comes from the low log2(XLEN) bits of rs2.
Rotates wrap shifted-out bits around to the other end; they are not logical shifts.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «ror x10, x11, x12 ; x10 = rotr(x11, x12 & (XLEN-1))».
Crypto & Security
Understand this scenario with real code like «ror x10, x11, x12 ; x10 = rotr(x11, x12 & (XLEN-1))».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: integer registers x0–x31; no immediate or rs3 operand.
- 32-bit OP: opcode=0110011, funct7=0110000, funct3=101; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV32/RV64; requires enabled Zbb or Zbkb; B includes Zbb.
- Rotate right within XLEN bits by rs2[4:0] in RV32 or rs2[5:0] in RV64; a zero amount preserves the source bit pattern.
- x0 is always zero and discards writes; rd may overlap a source, using source values before writeback. Only integer registers are operated on, with no data-memory access.
Pitfalls / Common Confusions
Shift amount is modulo XLEN
FAQ
What is the result width of ROR?
ROR rotates at the complete XLEN width and writes an equally wide result to rd: rs2[4:0] in RV32 and rs2[5:0] in RV64.