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RORW

RISC-V RORW Instruction Details

Instruction ManualR-type

Rotate right word by register (RV64)

Instruction Syntax

rorw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbBit Manipulation
Related Search Terms
rorw instructionRISC-V rorwrorw syntaxrorw encodingrotate-right word and sign-extendrorw Zbb

Instruction Behavior

Rotates lower 32 bits of rs1 right by rs2[4:0], result sign-extended to XLEN. Part of Zbb and Zbkb.

Quick Understanding & Search Notes

RORW is a B/Zbb instruction for rotate-right word and sign-extend. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.

The W-suffixed form operates only on the low 32 bits of rs1 and uses a 5-bit amount.
The 32-bit result is sign-extended from bit 31 to XLEN; it is not an ordinary 64-bit rotate.
RISC-V Unprivileged ISA Manual: B bit-manipulation extension

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «rorw x10, x11, x12 ; x10 = sign_ext(rotr(x11[31:0], x12[4:0]))».

Crypto & Security

Understand this scenario with real code like «rorw x10, x11, x12 ; x10 = sign_ext(rotr(x11[31:0], x12[4:0]))».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

RV64 only
Operates on lower 32 bits
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
They exist in RV64/RV128-like environments, not RV32.

FAQ

Does RORW access memory?

No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.

What is the result width of RORW?

Except that W-suffixed forms produce a 32-bit result then sign-extend and .uw forms first extract a 32-bit unsigned operand, the result is written to rd at XLEN width.