Does RORW access memory?
It does not access data memory; it reads integer source registers and writes the computed result to rd.
RORW
RISC-V RORW Instruction Details
Instruction ManualR-typeRotate right word by register (RV64)
Instruction Syntax
rorw rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: integer registers x0–x31; rs2[4:0] supplies the rotate amount, with no immediate.
32-bit OP-32: opcode=0111011, funct3=101, funct7=0110000; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV64 only; requires enabled Zbb or Zbkb; B includes Zbb.
Rotate right within rs1[31:0], then sign-extend result bit31 to 64 bits, including when the rotate amount is zero.
x0 is always zero and discards writes; rd may overlap a source, using values before writeback. Only integer registers are operated on, with no data-memory access.
BZbbZbkbBit Manipulation
Instruction Behavior
RV64 only: rotate rs1[31:0] right by rs2[4:0], then sign-extend result bit 31 to XLEN. Requires Zbb or Zbkb.
RORW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
rorw
,
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
t1(x6)
0x0000000000000014
a0(x10)
0x0000000000001000
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
01010
rs2
00110
rs1
101
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x60A352BB
opcode
0111011 -> OP-32
funct3
101 -> RORW
funct7
0110000 -> RORW selector
rd / rs1 / rs2
t0(x5) / t1(x6)=0x00000014 / a0(x10)=0x0000000000001000
shamt
rs2[4:0]=00000 -> 0
32-bit rotate right
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x60A352BB
syntax : rorw t0(x5), t1(x6), a0(x10)
Result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
RORW is RV64-only: it rotates rs1[31:0] right by rs2[4:0], then sign-extends the result to XLEN.
The W-suffixed form operates only on the low 32 bits of rs1 and uses a 5-bit amount.
The 32-bit result is sign-extended from bit 31 to XLEN; it is not an ordinary 64-bit rotate.
Common Usage Scenarios
Rotate right
RV64 with Zbb (or Zbkb), x11=0x1234567880000001, x12=33: x12[4:0]=1, so rorw x10, x11, x12 writes x10=0xFFFFFFFFC0000000.
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: integer registers x0–x31; rs2[4:0] supplies the rotate amount, with no immediate.
- 32-bit OP-32: opcode=0111011, funct3=101, funct7=0110000; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV64 only; requires enabled Zbb or Zbkb; B includes Zbb.
- Rotate right within rs1[31:0], then sign-extend result bit31 to 64 bits, including when the rotate amount is zero.
- x0 is always zero and discards writes; rd may overlap a source, using values before writeback. Only integer registers are operated on, with no data-memory access.
Pitfalls / Common Confusions
RV64 only
Operates on lower 32 bits
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
RORW is an RV64 instruction; this W form does not exist in RV32.
FAQ
What is the result width of RORW?
RORW operates only on rs1[31:0] and writes rd after sign-extending bit 31 of the 32-bit result.