Does SM3P1 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SM3P1
RISC-V SM3P1 Instruction Details
Instruction ManualI-typeSM3 hash P1 permutation: P1(x) = x ^ ROTL(x,15) ^ ROTL(x,23)
Instruction Syntax
sm3p1 rd, rs1
rd and rs1 select integer x0–x31 or ABI names; there is no assembly immediate.
32-bit OP-IMM: bits31:20=000100001001, funct3=001, opcode=0010011.
RV32/RV64 Zksh; P1(x)=x^ROTL32(x,15)^ROTL32(x,23), x=rs1[31:0]. RV64 sign-extends the 32-bit result.
x0 sources are zero and writes to x0 are discarded; overlapping operands read values before writeback. Execution latency must be data-independent.
ZkshCrypto & Security
Related Search Terms
Instruction Behavior
sm3p1 is the Zksh SM3 hash P1 transform instruction. It implements P1(x) = x ^ ROTL(x, 15) ^ ROTL(x, 23): it reads the low 32 bits of rs1, computes the result, and writes rd; RV64 sign-extends that result to XLEN. P1 is a transform used by the SM3 hash function.
SM3P1 Decode And Execute Animation
Bounded teaching inputs execute the official SM3 fixed-width bit operations; this does not model a complete algorithm or microarchitecture.
rd
rs1
sm3p1
,
Initially rd shares the source value when rd=rs1; otherwise the demo starts rd at 0. An rs1=x0 source always reads 0. SM3P1 is defined in RV32/RV64; RV64 uses X(rs1)[31:0] and sign-extends the 32-bit result to XLEN.
fixed selector
source
fixed
destination
OP-IMM
31..20
000100001001
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
inb
0x89ABCDEF
rol32(inb, 15)
0xE6F7C4D5
rol32(inb, 23)
0xF7C4D5E6
result
0x9898DCDC
Architectural Result
a0(x10) = 0x00000000
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm, pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
SM3P1 applies P1(x)=x^ROTL32(x,15)^ROTL32(x,23) to rs1[31:0] and writes rd; RV64 sign-extends the result.
Performs the SM3 P1 transform from rs1[31:0] with rotate-left amounts 15 and 23; RV64 sign-extends the result.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
Common Usage Scenarios
Crypto & Security
RV32/RV64 Zksh, a1=1: P1(1)=1^0x00008000^0x00800000=0x00808001, written to a0.
Chinese National Crypto
RV32/RV64 Zksh, a1=1: P1(1)=1^0x00008000^0x00800000=0x00808001, written to a0.
Pre-Use Checklist
Syntax Check
- rd and rs1 select integer x0–x31 or ABI names; there is no assembly immediate.
- 32-bit OP-IMM: bits31:20=000100001001, funct3=001, opcode=0010011.
Semantic Check
- RV32/RV64 Zksh; P1(x)=x^ROTL32(x,15)^ROTL32(x,23), x=rs1[31:0]. RV64 sign-extends the 32-bit result.
- x0 sources are zero and writes to x0 are discarded; overlapping operands read values before writeback. Execution latency must be data-independent.
Pitfalls / Common Confusions
P1 differs from P0 in shift amounts: (15,23) vs (9,17).
Uses rotate-left (ROTL), not right shift.
FAQ
Is SM3P1 a complete algorithm implementation?
No. It implements only the SM3 P1 transform; software still combines the required operations for its SM3 algorithm flow.