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SSAMOSWAP.D

RISC-V SSAMOSWAP.D Instruction Details

Instruction ManualAMO-type

SSAMOSWAP.D is an RV64-only AMO-style swap on shadow-stack memory, returning the old value and storing the new value.

Instruction Syntax

ssamoswap.d rd, rs2, (rs1)
Operand Breakdown
rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.
rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.
rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.
AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.
ZicfissSecurity Mechanisms
Related Search Terms
ssamoswap.d instructionRISC-V ssamoswap.dssamoswap.d syntaxssamoswap.d encodingssamoswap.d shadow-stack atomic swapssamoswap.d CFIssamoswap.d shadow stack

Instruction Behavior

Beginner view: SSAMOSWAP.D atomically reads a value from the shadow-stack location addressed by rs1 into rd and writes the corresponding value from rs2 back to that address. It supports shadow-stack switching and checkpoint maintenance.

SSAMOSWAP.D Decode & Execute Animation

Shows only specification-defined encodings, conditions, and architectural state; it does not model pipelines, cache coherence, or platform policy.

ssamoswap.d a0, a2, (a1)
Execution Context
Instruction Encoding
31..27
funct5
01001
26
aq
0
25
rl
0
24..20
rs2
a2
19..15
rs1
a1
14..12
funct3
011
11..7
rd
a0
6..0
opcode
0101111 (AMO)
Decode fixed fields
Fixed encoding fields identify the instruction and operand roles.
Atomic swap: x[a0] <- mem[0x0000000000003000] = 0x1122334455667788; mem <- 0xAABBCCDDEEFF0011.
Architectural state has not been committed.

Quick Understanding & Search Notes

SSAMOSWAP.D is an RV64 Zicfiss AMO: it atomically loads the old doubleword into rd, then stores rs2's doubleword at the shadow-stack location addressed by rs1.

SSAMOSWAP.W/D use AMO-style read-old/write-new behavior and may use aq/rl consistency semantics.
It does not use a Zimop/Zcmop fallback: SSAMOSWAP.W/D execution is also constrained by SSE control and shadow-stack memory-protection conditions.
RISC-V Unprivileged ISA Manual: Control-Flow IntegrityRISC-V Unprivileged ISA Manual: Zimop/Zcmop May-Be-Operations

Common Usage Scenarios

Data Loading

Understand this scenario with real code like «ssamoswap.d t0, t1, (t2)».

Resource Management

Understand this scenario with real code like «ssamoswap.d t0, t1, (t2)».

Stack & Frame

Understand this scenario with real code like «ssamoswap.d t0, t1, (t2)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is AMO-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

SSAMOSWAP.D does not use a Zimop/Zcmop MOP-compatible no-op; outside M-mode, failed SSE access checks raise illegal-instruction or virtual-instruction exceptions, while an M-mode access raises a store/AMO access-fault.
The address must refer to valid shadow-stack memory and be naturally aligned to the operand width; otherwise shadow-stack memory-protection rules apply.
It is an AMO-like operation with aq/rl release-consistency semantics; do not treat it as an ordinary load/store.
On RV64, SSAMOSWAP.W sign-extends the loaded 32-bit old value to rd; .D is RV64-only.

FAQ

What happens if the related CFI feature is inactive for SSAMOSWAP.D?

SSAMOSWAP.D does not use a Zimop/Zcmop fallback; its execution follows SSE access-control and shadow-stack memory-protection rules, which can raise illegal-instruction, virtual-instruction, or store/AMO access-fault exceptions depending on privilege and state.

What official rule defines SSAMOSWAP.D?

The Control-Flow Integrity chapter of the RISC-V Unprivileged ISA defines LPAD, SSPUSH, SSPOPCHK, SSRDP, and SSAMOSWAP.