Check vl first
Body elements satisfy vstart ≤ i < vl; vstart≥vl leaves the destination unchanged. Set supported vl/vtype and initialize the sources and v0 first.
VADC.VVM
RISC-V VADC.VVM Instruction Details
Instruction ManualOP-VAdd both sources and the v0 carry-in bit for every body element; write the low SEW bits to vd.
Instruction Syntax
vadc.vvm vd, vs2, vs1, v0
Operand Breakdown
vd and vs2 are SEW-wide vector register groups; equal vector sources read identical initial elements, and same-EEW destination/source overlap is permitted.
vs1 is the second SEW-wide vector source, not an integer scalar register.
vm=0 is fixed and vm=1 is reserved; v0.mask[i] is arithmetic carry-in, all body elements execute, and vd cannot be v0.
Require V and the selected vtype. Body elements satisfy vstart ≤ i < vl; results wrap at SEW and tails follow vta. v0 cannot be read at both EEW=1 and SEW; masked vd cannot overwrite v0.
VVector Operations
Instruction Behavior
V 1.0, RV32/RV64, with supported vtype. Every body element (vstart ≤ i < vl) writes the low SEW bits of vs2[i] + vs1[i] + v0.mask[i]. vm=0 is fixed; vm=1 and vd=v0 are reserved. A zero carry bit does not disable execution. v0 cannot also supply SEW data. Tails follow vta; vstart≥vl leaves vd unchanged. VMADC produces carry-out.
VADC.VVM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VADC uses each v0 bit as carry-in, performs SEW-width add-with-carry, and writes the sum.
Instruction input
vadc.vvm
v0
v0
arithmetic input, not execution maskRequire valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvadc.vvm
funct6
010000
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+cin
+cin
+cin
+cin
+cin
+cin
+cin
+cin
v12
0x0003
0x0016
0x001f
0x0006
0x0031
0x003a
0x0005
0x004c
cin
1
0
1
1
1
0
1
1
v4
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vadc.vvm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer add-with-carry, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VADC is the data-result instruction for multiword addition: v0 supplies the input bit, vd stores the low SEW-bit result, and VMADC generates the output bit.
32-bit OP-V: opcode=1010111, funct6=010000, funct3=000, with vm fixed to 0.
VADC.VVM uses the corresponding v0 mask bit as carry-in; this is not ordinary v0.t masked execution.
Destination vd is an ordinary vector result; the integer result is truncated to SEW and the output bit is not written by this instruction.
The official V extension reserves encodings where VADC has vd equal to v0.
Vector Execution Context
When reading VADC.VVM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
vm=0 is fixed and vm=1 reserved; v0 supplies carry-in and all body elements execute. Tails follow vta.
Common Usage Scenarios
Multi-word Integer Addition
Assume V with e8,m1, vl=4, vstart=0, all vs2 elements=255, all vs1 elements=1, and v0 bits 1010 in lane order 0..3. The example vadc.vvm v4, v8, v12, v0 gives [1,0,1,0]; a zero v0 bit still executes addition, and tails follow vta.
Per-element Carry Input
Assume V with e8,m1, vl=4, vstart=0, all vs2 elements=255, all vs1 elements=1, and v0 bits 1010 in lane order 0..3. The example vadc.vvm v4, v8, v12, v0 gives [1,0,1,0]; a zero v0 bit still executes addition, and tails follow vta.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector register groups; equal vector sources read identical initial elements, and same-EEW destination/source overlap is permitted.
- vs1 is the second SEW-wide vector source, not an integer scalar register.
Semantic Check
- vm=0 is fixed and vm=1 is reserved; v0.mask[i] is arithmetic carry-in, all body elements execute, and vd cannot be v0.
- Require V and the selected vtype. Body elements satisfy vstart ≤ i < vl; results wrap at SEW and tails follow vta. v0 cannot be read at both EEW=1 and SEW; masked vd cannot overwrite v0.
Pitfalls / Common Confusions
In VADC.VVM, v0 is carry-in arithmetic input, not an ordinary masked-execution element enable.
VADC writes only the low SEW-bit sum; it does not write a carry mask. Use VMADC.
VADC cannot encode vd as v0 because v0 is fixed as carry-in input.
FAQ
Is v0 an execution mask in VADC.VVM?
No. The corresponding v0 bit is carry-in arithmetic input.
What result does VADC.VVM write?
It writes the low SEW-bit sum; carry-out is generated by VMADC.