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VADC.VVM

RISC-V VADC.VVM Instruction Details

Instruction ManualR-type

Vector add with carry-in: vd[i] = vs2[i] + vs1[i] + v0[i].LSB; use vmadc to generate carry-out.

Instruction Syntax

vadc.vvm vd, vs2, vs1, v0
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Related Search Terms
VADC.VVM instructionRISC-V VADC.VVMvadc.vvm syntaxvadc.vvm encodingvadc.vvm Vvadc.vvm vectorvector add with carry

Instruction Behavior

vadc.vvm is the vector-vector add-with-carry instruction. For each element it computes vd[i] = vs2[i] + vs1[i] + v0[i].LSB, with carry-in from the corresponding mask bit in v0. The sum is written to the regular vector destination vd; this instruction does not produce a carry-out mask. Use vmadc.vvm to compute carry-out. SEW supports 8/16/32/64.

Quick Understanding & Search Notes

VADC.VVM is an RVV add-with-carry sum instruction for multi-word arithmetic. Carry-in comes from v0.mask[i], the sum is written to normal vector register vd, and carry-out must be generated separately with VMADC.

VADC is encoded as a masked (vm=0) form, but it operates on and writes all body elements; vm=1 unmasked encodings are reserved.
Correct carry propagation usually uses vmadc first to generate a temporary carry mask, then vadc for the sum.
RISC-V Unprivileged ISA Manual, V Extension

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vadc.vvm vd, vs2, vs1, v0».

Data Storing

Understand this scenario with real code like «vadc.vvm vd, vs2, vs1, v0».

Vector Operations

Understand this scenario with real code like «vadc.vvm vd, vs2, vs1, v0».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

v0.mask[i] is carry-in, not an element execution mask.
VADC writes the sum, not carry-out; use VMADC for carry-out.
VADC is encoded as a masked form but writes all body elements; vm=1 encodings are reserved.

FAQ

Is v0 an ordinary execution mask here?

Here each v0 mask bit is the carry-in, not an element enable bit.

Does VADC produce the next carry?

No. VADC writes the sum; VMADC produces the carry mask for the next step.