VADC.VXM

RISC-V VADC.VXM Instruction Details

Instruction ManualR-type

Add each vs2 element with scalar rs1 and carry-in from v0: vd[i]=vs2[i]+x[rs1]+v0.mask[i].

Instruction Syntax

vadc.vxm vd, vs2, rs1, v0
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector OperationsInteger Arithmetic

Instruction Behavior

VADC.VXM performs vector-scalar add with carry: vd[i] = vs2[i] + x[rs1] + v0.mask[i]. The corresponding v0 mask bit is carry-in, not an element execution mask; VADC is encoded as a masked form but writes all body elements. Use VMADC to generate carry-out.

Quick Understanding & Search Notes

VADC.VXM is an RVV add-with-carry sum instruction for multi-word arithmetic. Carry-in comes from v0.mask[i], the sum is written to normal vector register vd, and carry-out must be generated separately with VMADC.

VADC is encoded as a masked (vm=0) form, but it operates on and writes all body elements; vm=1 unmasked encodings are reserved.
Correct carry propagation usually uses vmadc first to generate a temporary carry mask, then vadc for the sum.

Common Usage Scenarios

Multi-precision Arithmetic

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmadc.vim v0, v8, 0 vadc.vxm v10, v8, a1, v0».

Big Integer Add

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmadc.vim v0, v8, 0 vadc.vxm v10, v8, a1, v0».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

v0.mask[i] is carry-in, not an element execution mask.
VADC writes the sum, not carry-out; use VMADC for carry-out.
VADC is encoded as a masked form but writes all body elements; vm=1 encodings are reserved.

FAQ

Is v0 an ordinary execution mask here?

Here each v0 mask bit is the carry-in, not an element enable bit.

Does VADC produce the next carry?

No. VADC writes the sum; VMADC produces the carry mask for the next step.