Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMADC.VXM
RISC-V VMADC.VXM Instruction Details
Instruction ManualR-typeVMADC computes each body element's carry-out and writes the Boolean result to the destination mask register.
Instruction Syntax
vmadc.vxm vd, vs2, rs1, v0
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerCarry/Borrow
Instruction Behavior
VMADC.VXM is the RISC-V V extension vector-scalar add carry-out instruction. It does not write a SEW-width integer result. For each body element within the current vl, it computes the carry-out of vs2 + the second source + v0[i] and writes one destination mask bit. v0 is carry-in arithmetic input, not an ordinary v0.t execution mask.
VMADC.VXM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMADC uses each v0 bit as carry-in and writes each carry-out as a destination mask bit.
Instruction input
vmadc.vxm
v0
v0
arithmetic input, not execution maskOP-V encodingvmadc.vxm
funct6
010001
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+cin
+cin
+cin
+cin
+cin
+cin
+cin
+cin
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
cin
1
0
1
1
1
0
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmadc.vxm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMADC generates carry bits for multiword addition: v0 supplies the input bit and vd.mask[i] stores the output bit.
OP-V encoding uses funct6=010001 and funct3 selects the .vv/.vx/.vi form.
VMADC.VXM uses the corresponding v0 mask bit as carry-in; this is not ordinary v0.t masked execution.
Destination vd is a mask result, one bit per body element.
VMADC pairs with VADC for multiword addition chains.
Vector Execution Context
When reading VMADC.VXM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Multi-Precision Add
Understand this scenario with real code like «vmadc.vxm v1, v2, a1, v0».
BigInt
Understand this scenario with real code like «vmadc.vxm v1, v2, a1, v0».
Carry Propagation
Understand this scenario with real code like «vmadc.vxm v1, v2, a1, v0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
In VMADC.VXM, v0 is carry-in arithmetic input, not an ordinary masked-execution element enable.
VMADC writes destination mask bits, not ordinary SEW-width vector elements.
Each VMADC mask result is a one-bit predicate, not a SEW-width integer value.
FAQ
Is v0 an execution mask in VMADC.VXM?
No. The corresponding v0 bit is carry-in arithmetic input.
What result does VMADC.VXM write?
It writes one destination mask bit for carry-out.