Is v0 an execution mask in VMADC.VXM?
No. The corresponding v0 bit is carry-in arithmetic input.
VMADC.VXM
RISC-V VMADC.VXM Instruction Details
Instruction ManualOPIVXVMADC computes each body element's carry-out and writes the Boolean result to the destination mask register.
Instruction Syntax
vmadc.vxm vd, vs2, rs1, v0
Operand Breakdown
32-bit OP-V: opcode=1010111, funct6=010001, funct3=100 (OPIVX), vm=0. vd is a single mask destination with one bit per element; vs2 is the SEW data source.
rs1 selects an integer register: use low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW. x0 supplies zero.
Fixed vm=0 uses v0 bit i as carry-in arithmetic input. All body elements execute, including where v0[i]=0. Syntax uses v0, not v0.t.
Add both SEW-bit sources as unsigned values and add v0[i]; vd.mask[i]=1 iff the sum≥2^SEW, otherwise 0. No SEW-wide sum is written; mask bit i is vd bit i, independent of SEW/LMUL.
Source/destination register-group overlap rules apply: masks have EEW=1; a narrower destination must start at the source group's low end. With carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0. The animation fixes LMUL=m1, so vd may equal a data source.
Require V 1.0, enabled vector state, valid vtype, and support for the selected width. Body is vstart≤i<vl; prestart stays unchanged and mask tails are always agnostic, regardless of vta. VL=0 or vstart≥vl updates no destination bits, including tails. The animation fixes VLEN=4096 and vstart=0 and shows only body bits.
VVector IntegerCarry/Borrow
Instruction Behavior
VMADC.VXM is the RISC-V V extension vector-scalar add carry-out instruction. It fixes vm=0 and does not write a SEW-width integer result. Every body element writes the carry-out of vs2[i] + x[rs1] + v0[i] as one destination mask bit. When XLEN is greater than SEW, the scalar uses its low SEW bits; when XLEN is less than SEW, it is sign-extended to SEW. v0 is carry-in arithmetic input, not an ordinary v0.t execution mask, so a body element still executes when v0[i] is 0.
VMADC.VXM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMADC uses each v0 bit as carry-in and writes each carry-out as a destination mask bit.
Instruction input
vmadc.vxm
v0
v0
arithmetic input, not execution maskExecution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMADC mask destinations are always tail-agnostic; tails are not guaranteed to be preserved, while VL=0 updates no destination bits, including tails. With LMUL=m1, vd may equal a SEW data source; with carry-in, v0 cannot also be a SEW data source, but vd may be v0. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmadc.vxm
funct6
010001
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+cin
+cin
+cin
+cin
+cin
+cin
+cin
+cin
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
cin
1
0
1
1
1
0
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmadc.vxm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMADC generates carry bits for multiword addition: v0 supplies the input bit and vd.mask[i] stores the output bit.
OP-V encoding uses funct6=010001 and funct3 selects the .vv/.vx/.vi form.
VMADC.VXM uses the corresponding v0 mask bit as carry-in; this is not ordinary v0.t masked execution.
Destination vd is a mask result, one bit per body element.
VMADC pairs with VADC for multiword addition chains.
Body elements satisfy vstart ≤ i < vl. Mask destinations are always tail-agnostic; VL=0 or vstart≥vl updates no destination bits, including tails.
Each mask result occupies one bit. Source/destination register-group overlap rules apply; with carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0.
Vector Execution Context
32-bit OP-V: opcode=1010111, funct6=010001, funct3=100 (OPIVX), vm=0. vd is a single mask destination with one bit per element; vs2 is the SEW data source.
rs1 selects an integer register: use low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW. x0 supplies zero.
Fixed vm=0 uses v0 bit i as carry-in arithmetic input. All body elements execute, including where v0[i]=0. Syntax uses v0, not v0.t.
Add both SEW-bit sources as unsigned values and add v0[i]; vd.mask[i]=1 iff the sum≥2^SEW, otherwise 0. No SEW-wide sum is written; mask bit i is vd bit i, independent of SEW/LMUL.
Source/destination register-group overlap rules apply: masks have EEW=1; a narrower destination must start at the source group's low end. With carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0. The animation fixes LMUL=m1, so vd may equal a data source.
Require V 1.0, enabled vector state, valid vtype, and support for the selected width. Body is vstart≤i<vl; prestart stays unchanged and mask tails are always agnostic, regardless of vta. VL=0 or vstart≥vl updates no destination bits, including tails. The animation fixes VLEN=4096 and vstart=0 and shows only body bits.
Common Usage Scenarios
Multi-Precision Add
Assume V, valid e8,m1, vl=1, vstart=0 and initialized sources: vs2[0]=255 and the second source is 1, with v0.mask[0]=1. The sum is 257, so destination mask bit 0 is 1. No integer sum is written and tails are not guaranteed to be preserved.
BigInt
Assume V, valid e8,m1, vl=1, vstart=0 and initialized sources: vs2[0]=255 and the second source is 1, with v0.mask[0]=1. The sum is 257, so destination mask bit 0 is 1. No integer sum is written and tails are not guaranteed to be preserved.
Carry Propagation
Assume V, valid e8,m1, vl=1, vstart=0 and initialized sources: vs2[0]=255 and the second source is 1, with v0.mask[0]=1. The sum is 257, so destination mask bit 0 is 1. No integer sum is written and tails are not guaranteed to be preserved.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V: opcode=1010111, funct6=010001, funct3=100 (OPIVX), vm=0. vd is a single mask destination with one bit per element; vs2 is the SEW data source.
- rs1 selects an integer register: use low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW. x0 supplies zero.
Semantic Check
- Fixed vm=0 uses v0 bit i as carry-in arithmetic input. All body elements execute, including where v0[i]=0. Syntax uses v0, not v0.t.
- Add both SEW-bit sources as unsigned values and add v0[i]; vd.mask[i]=1 iff the sum≥2^SEW, otherwise 0. No SEW-wide sum is written; mask bit i is vd bit i, independent of SEW/LMUL.
- Source/destination register-group overlap rules apply: masks have EEW=1; a narrower destination must start at the source group's low end. With carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0. The animation fixes LMUL=m1, so vd may equal a data source.
- Require V 1.0, enabled vector state, valid vtype, and support for the selected width. Body is vstart≤i<vl; prestart stays unchanged and mask tails are always agnostic, regardless of vta. VL=0 or vstart≥vl updates no destination bits, including tails. The animation fixes VLEN=4096 and vstart=0 and shows only body bits.
Pitfalls / Common Confusions
In VMADC.VXM, v0 is carry-in arithmetic input, not an ordinary masked-execution element enable.
VMADC writes destination mask bits, not ordinary SEW-width vector elements.
Each VMADC mask result is a one-bit predicate, not a SEW-width integer value.
FAQ
What result does VMADC.VXM write?
It writes one destination mask bit for carry-out.