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VMADC.VV

RISC-V VMADC.VV Instruction Details

Instruction ManualR-type

Compute element-wise add carry-out and write the Boolean result to mask destination vd.

Instruction Syntax

vmadc.vv vd, vs2, vs1
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerCarry/Borrow
Related Search Terms
VMADC.VV instructionRISC-V VMADC.VVvmadc.vv syntaxvmadc.vv RVVcarry outmask result

Instruction Behavior

VMADC.VV is a RISC-V V vector add carry-out instruction. It does not write the integer sum or difference; it writes each element's carry-out as a destination mask bit. The form without the m suffix has no carry input and no ordinary execution-mask operand. The destination is a mask register, not an ordinary SEW-width integer result.

Quick Understanding & Search Notes

VMADC.VV generates a carry mask; in m forms, v0 is the carry/borrow input, not an ordinary execution mask.

Destination vd holds a one-bit mask result, one bit per element.
Forms without the m suffix do not read v0 as carry/borrow input.
Pair with VADC/VSBC for multiword add/subtract.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMADC.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Multi-Precision Add

Understand this scenario with real code like «vmadc.vv v1, v2, v3».

BigInt

Understand this scenario with real code like «vmadc.vv v1, v2, v3».

Carry Propagation

Understand this scenario with real code like «vmadc.vv v1, v2, v3».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Carry is a single mask bit, not full SEW value
No carry-in in the non-m form; distinguish from vmadc.vvm (carry-in, vm=0)

FAQ

Does VMADC.VV write the add/subtract result?

No. It writes only carry or borrow mask bits; data results come from instructions such as VADC/VSBC.