Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMADC.VV
RISC-V VMADC.VV Instruction Details
Instruction ManualOPIVVCompute element-wise add carry-out and write the Boolean result to mask destination vd.
Instruction Syntax
vmadc.vv vd, vs2, vs1
Operand Breakdown
vd: mask destination register, with one carry-out result bit per body element.
vs2 and vs1: same-lane elements are added at the current SEW.
vm: fixed to vm=1; it reads no v0 carry-in and vm is not a syntax operand.
VVector IntegerCarry/Borrow
Instruction Behavior
VMADC.VV is a RISC-V V vector add carry-out instruction. It does not write the integer sum; it writes the carry-out of vs2[i] + vs1[i] for each element as a destination mask bit. The form without the m suffix has no carry input and no ordinary execution-mask operand. The destination is a mask register, not an ordinary SEW-width integer result.
VMADC.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how a non-m VMADC form uses vm=1 for all body elements, reads no carry-in, and writes each carry-out to a destination mask bit.
Instruction input
vmadc.vv
vm
1
fixed unmasked encoding, not a syntax operandThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. VMADC.VV fixes vm=1, reads no v0 input, and produces one destination-mask bit for each body element.
OP-V encodingvmadc.vv
funct6
010001
vm
1
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+
+
+
+
+
+
+
+
v12
0x0003
0x0016
0x001f
0x0006
0x0031
0x003a
0x0005
0x004c
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmadc.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMADC.VV fixes vm=1 and generates a carry mask from vs2[i] + vs1[i] for every body element; it does not read v0.
Destination vd holds a one-bit mask result, one bit per element.
This non-m form fixes vm=1, reads no v0, and has no ordinary execution-mask operand.
Pair it with a carry-in VADC form for multiword addition.
Vector Execution Context
When reading VMADC.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Multi-Precision Add
Understand this scenario with real code like «vmadc.vv v1, v2, v3».
BigInt
Understand this scenario with real code like «vmadc.vv v1, v2, v3».
Carry Propagation
Understand this scenario with real code like «vmadc.vv v1, v2, v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Carry is a single mask bit, not full SEW value
No carry-in in the non-m form; distinguish from vmadc.vvm (carry-in, vm=0)
FAQ
Does VMADC.VV write the addition result?
No. It writes only carry-out mask bits; an SEW-wide sum comes from a data instruction such as VADC.