Does VMADC.VX write the addition result?
No. It writes only carry-out mask bits; an SEW-wide sum comes from a data instruction such as VADC.
VMADC.VX
RISC-V VMADC.VX Instruction Details
Instruction ManualOPIVXCompute element-wise add carry-out and write the Boolean result to mask destination vd.
Instruction Syntax
vmadc.vx vd, vs2, rs1
Operand Breakdown
32-bit OP-V: opcode=1010111, funct6=010001, funct3=100 (OPIVX), vm=1. vd is a single mask destination with one bit per element; vs2 is the SEW data source.
rs1 selects an integer register: use low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW. x0 supplies zero.
Fixed vm=1 has no carry-in and no ordinary v0.t execution mask. All body elements execute.
Add both SEW-bit sources as unsigned values; vd.mask[i]=1 iff the sum≥2^SEW, otherwise 0. No SEW-wide sum is written; mask bit i is vd bit i, independent of SEW/LMUL.
Source/destination register-group overlap rules apply: masks have EEW=1; a narrower destination must start at the source group's low end. With carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0. The animation fixes LMUL=m1, so vd may equal a data source.
Require V 1.0, enabled vector state, valid vtype, and support for the selected width. Body is vstart≤i<vl; prestart stays unchanged and mask tails are always agnostic, regardless of vta. VL=0 or vstart≥vl updates no destination bits, including tails. The animation fixes VLEN=4096 and vstart=0 and shows only body bits.
VVector IntegerCarry/Borrow
Instruction Behavior
VMADC.VX is a RISC-V V vector-scalar add carry-out instruction. It does not write the integer sum; it writes the carry-out of vs2[i] + x[rs1] for each element as a destination mask bit. When XLEN is greater than SEW, the scalar uses its low SEW bits; when XLEN is less than SEW, it is sign-extended to SEW. The form without the m suffix has no carry input and no ordinary execution-mask operand. The destination is a mask register, not an ordinary SEW-width integer result.
VMADC.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how a non-m VMADC form uses vm=1 for all body elements, reads no carry-in, and writes each carry-out to a destination mask bit.
Instruction input
vmadc.vx
vm
1
fixed unmasked encoding, not a syntax operandExecution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMADC mask destinations are always tail-agnostic; tails are not guaranteed to be preserved, while VL=0 updates no destination bits, including tails. With LMUL=m1, vd may equal a SEW data source; with carry-in, v0 cannot also be a SEW data source, but vd may be v0. VMADC.VX fixes vm=1 with no v0 carry-in; when v0 is specified as a SEW data source, its data is still read. Each body element produces one destination-mask bit.
OP-V encodingvmadc.vx
funct6
010001
vm
1
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+
+
+
+
+
+
+
+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmadc.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, fixed vm=1 with no carry-in, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMADC.VX fixes vm=1 and generates a carry mask from vs2[i] + x[rs1] for every body element; it reads no v0 carry-in, but still reads v0 when specified as a SEW data source.
Destination vd holds a one-bit mask result, one bit per element.
This non-m form fixes vm=1, reads no v0 carry-in, and has no ordinary execution-mask operand; v0 may still be a SEW data source.
Pair it with a carry-in VADC form for multiword addition.
Body elements satisfy vstart ≤ i < vl. Mask destinations are always tail-agnostic; VL=0 or vstart≥vl updates no destination bits, including tails.
Each mask result occupies one bit. Source/destination register-group overlap rules apply; with carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0.
Vector Execution Context
32-bit OP-V: opcode=1010111, funct6=010001, funct3=100 (OPIVX), vm=1. vd is a single mask destination with one bit per element; vs2 is the SEW data source.
rs1 selects an integer register: use low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW. x0 supplies zero.
Fixed vm=1 has no carry-in and no ordinary v0.t execution mask. All body elements execute.
Add both SEW-bit sources as unsigned values; vd.mask[i]=1 iff the sum≥2^SEW, otherwise 0. No SEW-wide sum is written; mask bit i is vd bit i, independent of SEW/LMUL.
Source/destination register-group overlap rules apply: masks have EEW=1; a narrower destination must start at the source group's low end. With carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0. The animation fixes LMUL=m1, so vd may equal a data source.
Require V 1.0, enabled vector state, valid vtype, and support for the selected width. Body is vstart≤i<vl; prestart stays unchanged and mask tails are always agnostic, regardless of vta. VL=0 or vstart≥vl updates no destination bits, including tails. The animation fixes VLEN=4096 and vstart=0 and shows only body bits.
Common Usage Scenarios
Multi-Precision Add
Assume V, valid e8,m1, vl=1, vstart=0 and initialized sources: vs2[0]=255 and the second source is 1. The sum is 256, so destination mask bit 0 is 1. No integer sum is written and tails are not guaranteed to be preserved.
BigInt
Assume V, valid e8,m1, vl=1, vstart=0 and initialized sources: vs2[0]=255 and the second source is 1. The sum is 256, so destination mask bit 0 is 1. No integer sum is written and tails are not guaranteed to be preserved.
Carry Propagation
Assume V, valid e8,m1, vl=1, vstart=0 and initialized sources: vs2[0]=255 and the second source is 1. The sum is 256, so destination mask bit 0 is 1. No integer sum is written and tails are not guaranteed to be preserved.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V: opcode=1010111, funct6=010001, funct3=100 (OPIVX), vm=1. vd is a single mask destination with one bit per element; vs2 is the SEW data source.
- rs1 selects an integer register: use low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW. x0 supplies zero.
Semantic Check
- Fixed vm=1 has no carry-in and no ordinary v0.t execution mask. All body elements execute.
- Add both SEW-bit sources as unsigned values; vd.mask[i]=1 iff the sum≥2^SEW, otherwise 0. No SEW-wide sum is written; mask bit i is vd bit i, independent of SEW/LMUL.
- Source/destination register-group overlap rules apply: masks have EEW=1; a narrower destination must start at the source group's low end. With carry-in, v0 cannot also be a SEW data source, but the mask destination may be v0. The animation fixes LMUL=m1, so vd may equal a data source.
- Require V 1.0, enabled vector state, valid vtype, and support for the selected width. Body is vstart≤i<vl; prestart stays unchanged and mask tails are always agnostic, regardless of vta. VL=0 or vstart≥vl updates no destination bits, including tails. The animation fixes VLEN=4096 and vstart=0 and shows only body bits.
Pitfalls / Common Confusions
No carry-in in the non-m form; for carry-in use vmadc.vxm (vm=0)
Carry is single mask bit, not full data value