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VMADC.VX

RISC-V VMADC.VX Instruction Details

Instruction ManualOPIVX

Compute element-wise add carry-out and write the Boolean result to mask destination vd.

Instruction Syntax

vmadc.vx vd, vs2, rs1
Operand Breakdown
vd: mask destination register, with one carry-out result bit per body element.
vs2 and x[rs1]: use the scalar's low SEW bits when XLEN is greater than SEW, or sign-extend it to SEW when XLEN is less than SEW.
vm: fixed to vm=1; it reads no v0 carry-in and vm is not a syntax operand.
VVector IntegerCarry/Borrow
Related Search Terms
VMADC.VX instructionRISC-V VMADC.VXvmadc.vx syntaxvmadc.vx RVVcarry outmask result

Instruction Behavior

VMADC.VX is a RISC-V V vector-scalar add carry-out instruction. It does not write the integer sum; it writes the carry-out of vs2[i] + x[rs1] for each element as a destination mask bit. When XLEN is greater than SEW, the scalar uses its low SEW bits; when XLEN is less than SEW, it is sign-extended to SEW. The form without the m suffix has no carry input and no ordinary execution-mask operand. The destination is a mask register, not an ordinary SEW-width integer result.

VMADC.VX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how a non-m VMADC form uses vm=1 for all body elements, reads no carry-in, and writes each carry-out to a destination mask bit.

Instruction input
vmadc.vx
vm
1
fixed unmasked encoding, not a syntax operand

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. VMADC.VX fixes vm=1, reads no v0 input, and produces one destination-mask bit for each body element.

OP-V encodingvmadc.vx
funct6
010001
vm
1
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+
+
+
+
+
+
+
+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step

Show OP-V 32-bit encoding fields

vmadc.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMADC.VX fixes vm=1 and generates a carry mask from vs2[i] + x[rs1] for every body element; it does not read v0.

Destination vd holds a one-bit mask result, one bit per element.
This non-m form fixes vm=1, reads no v0, and has no ordinary execution-mask operand.
Pair it with a carry-in VADC form for multiword addition.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMADC.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Multi-Precision Add

Understand this scenario with real code like «vmadc.vx v1, v2, a1».

BigInt

Understand this scenario with real code like «vmadc.vx v1, v2, a1».

Carry Propagation

Understand this scenario with real code like «vmadc.vx v1, v2, a1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is OPIVX.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No carry-in in the non-m form; for carry-in use vmadc.vxm (vm=0)
Carry is single mask bit, not full data value

FAQ

Does VMADC.VX write the addition result?

No. It writes only carry-out mask bits; an SEW-wide sum comes from a data instruction such as VADC.