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VMADC.VVM

RISC-V VMADC.VVM Instruction Details

Instruction ManualOPIVV

VMADC computes each body element's carry-out and writes the Boolean result to the destination mask register.

Instruction Syntax

vmadc.vvm vd, vs2, vs1, v0
Operand Breakdown
vd: mask destination register, with one carry-out result bit per body element.
vs2 and vs1: same-lane elements are added at the current SEW.
vm: fixed to vm=0; the corresponding v0 mask bit is a 0/1 carry-in arithmetic input and does not disable a body element.
VVector IntegerCarry/Borrow
Related Search Terms
vmadc.vvm instructionRISC-V vmadc.vvmvmadc.vvm syntaxvmadc.vvm encodingRVV vector add carry-outvector vector carryv0 carry-in

Instruction Behavior

VMADC.VVM is the RISC-V V extension vector-vector add carry-out instruction. It fixes vm=0 and does not write a SEW-width integer result. Every body element writes the carry-out of vs2[i] + vs1[i] + v0[i] as one destination mask bit. v0 is carry-in arithmetic input, not an ordinary v0.t execution mask, so a body element still executes when v0[i] is 0.

VMADC.VVM Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMADC uses each v0 bit as carry-in and writes each carry-out as a destination mask bit.

Instruction input
vmadc.vvm
v0
v0
arithmetic input, not execution mask

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvmadc.vvm
funct6
010001
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+cin
+cin
+cin
+cin
+cin
+cin
+cin
+cin
v12
0x0003
0x0016
0x001f
0x0006
0x0031
0x003a
0x0005
0x004c
cin
1
0
1
1
1
0
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step

Show OP-V 32-bit encoding fields

vmadc.vvm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMADC generates carry bits for multiword addition: v0 supplies the input bit and vd.mask[i] stores the output bit.

OP-V encoding uses funct6=010001 and funct3 selects the .vv/.vx/.vi form.
VMADC.VVM uses the corresponding v0 mask bit as carry-in; this is not ordinary v0.t masked execution.
Destination vd is a mask result, one bit per body element.
VMADC pairs with VADC for multiword addition chains.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMADC.VVM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Multi-Precision Add

Understand this scenario with real code like «vmadc.vvm v1, v2, v3, v0».

BigInt

Understand this scenario with real code like «vmadc.vvm v1, v2, v3, v0».

Carry Propagation

Understand this scenario with real code like «vmadc.vvm v1, v2, v3, v0».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is OPIVV.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

In VMADC.VVM, v0 is carry-in arithmetic input, not an ordinary masked-execution element enable.
VMADC writes destination mask bits, not ordinary SEW-width vector elements.
Each VMADC mask result is a one-bit predicate, not a SEW-width integer value.

FAQ

Is v0 an execution mask in VMADC.VVM?

No. The corresponding v0 bit is carry-in arithmetic input.

What result does VMADC.VVM write?

It writes one destination mask bit for carry-out.