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VSBC.VXM

RISC-V VSBC.VXM Instruction Details

Q: Is v0 an execution mask in VSBC.VXM?

No. The corresponding v0 bit is borrow-in arithmetic input.

Q: What result does VSBC.VXM write?

It writes the low SEW-bit difference; borrow-out is generated by VMSBC.

Instruction ManualOPIVX

Compute vs2[i] − scalar − v0.mask[i] for every body element; write the low SEW-bit difference to vd.

Instruction Syntax

vsbc.vxm vd, vs2, rs1, v0

Operand Breakdown

vd/vs2 are SEW/LMUL vector groups; rs1 selects an integer scalar and x0 supplies zero. v0 supplies borrow-in; syntax uses no v0.t.

OPIVX: funct6=010010, funct3=100, opcode=1010111. Convert the scalar by XLEN/SEW truncation or sign-extension.

Every body element writes lowSEW(vs2[i]−scalar−v0.mask[i]). Fixed vm=0; vm=1 and vd=v0 encodings are reserved. v0 cannot also supply SEW data.

Require V 1.0, enabled vector state and valid vtype. Body is vstart≤i<vl; tails follow vta. vl=0 or vstart≥vl leaves vd unchanged.

VVector IntegerCarry/Borrow

Related Search Terms

vsbc.vxm instruction RISC-V vsbc.vxm vsbc.vxm syntax vsbc.vxm encoding RVV vector subtract with borrow vector scalar borrow v0 borrow-in

Instruction Behavior

VSBC.VXM is vector-scalar subtraction with borrow in V. v0 supplies borrow-in without disabling elements: every body element vstart≤i<vl executes. Results wrap at SEW; VMSBC generates borrow-out.

VSBC.VXM Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VSBC uses each v0 bit as borrow-in, performs SEW-width subtract-with-borrow, and writes the difference.

Instruction input

vsbc.vxm

vdUse v1-v31; v0 is reservedvs2Use v1-v31; v0 supplies EEW=1 borrow-inrs1Use x0-x31 or ABI name

arithmetic input, not execution mask

Scalar x[rs1]: XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends; x0 supplies zero.

Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. Fix VLEN=4096 and VLMAX=4096/16=256; equal-width sources/destination may overlap. Fix vm=0; vm=1 is reserved. v0 supplies borrow-in, every body element executes, and vd cannot be v0. When v0 supplies the EEW=1 mask/borrow bits it cannot also supply data. Enter nonnegative element bit patterns. VL=0 updates no destination bits. Only body is shown without definite inactive/tail values; teaching stages are not processor cycles.

Execution Context

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 borrow-in bitseach bit is a 0/1 arithmetic input

OP-V encodingvsbc.vxm

funct6

010010

vs2

01000

rs1

01011

funct3

100

00100

opcode

1010111

lane

0x0000

0x003b

0x004c

0x0003

0x006e

0x007f

0x0002

0x00a1

-bin

x11

0x0013

bin

...

Current step

Show OP-V 32-bit encoding fields

vsbc.vxm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows OP-V field decode, subtract-with-borrow, v0 borrow-in, and vd writeback; teaching stages are not processor cycles.

Quick Understanding & Search Notes

VSBC is the data-result instruction for multiword subtraction: v0 supplies the input bit, vd stores the low SEW-bit result, and VMSBC generates the output bit.

32-bit OP-V: opcode=1010111, funct6=010010, funct3=100 (OPIVX). Fixed vm=0; vm=1 is reserved.

XLEN>SEW takes low SEW bits of x[rs1]; XLEN<SEW sign-extends; x0 supplies zero.

vd cannot be v0. v0 cannot supply both EEW=1 borrow bits and SEW data. Equal-width source/destination overlap is legal.

Require V 1.0, enabled vector state and valid supported vtype/SEW. Prestart is unchanged; tails follow vta. vl=0 or vstart≥vl leaves vd unchanged.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (20260120), “V” 1.0

Vector Execution Context

vd/vs2 are SEW/LMUL vector groups; rs1 selects an integer scalar and x0 supplies zero. v0 supplies borrow-in; syntax uses no v0.t.

OPIVX: funct6=010010, funct3=100, opcode=1010111. Convert the scalar by XLEN/SEW truncation or sign-extension.

Every body element writes lowSEW(vs2[i]−scalar−v0.mask[i]). Fixed vm=0; vm=1 and vd=v0 encodings are reserved. v0 cannot also supply SEW data.

Require V 1.0, enabled vector state and valid vtype. Body is vstart≤i<vl; tails follow vta. vl=0 or vstart≥vl leaves vd unchanged.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Multi-Precision Sub

Assume enabled V/VS, valid m1, VLEN=4096, supported widths, vl=4, vstart=0 and initialized sources, XLEN=64. SEW=8, x5=1, v12=[0,1,255,7], v0.mask[0..3]=1010 → v8=[254,0,253,6]. Every body element executes; tails follow vta. vl=0 updates no destination.

BigInt

Pre-Use Checklist

Syntax Check

vd/vs2 are SEW/LMUL vector groups; rs1 selects an integer scalar and x0 supplies zero. v0 supplies borrow-in; syntax uses no v0.t.
OPIVX: funct6=010010, funct3=100, opcode=1010111. Convert the scalar by XLEN/SEW truncation or sign-extension.

Semantic Check

Every body element writes lowSEW(vs2[i]−scalar−v0.mask[i]). Fixed vm=0; vm=1 and vd=v0 encodings are reserved. v0 cannot also supply SEW data.
Require V 1.0, enabled vector state and valid vtype. Body is vstart≤i<vl; tails follow vta. vl=0 or vstart≥vl leaves vd unchanged.

Pitfalls / Common Confusions

In VSBC.VXM, v0 is borrow-in arithmetic input, not an ordinary masked-execution element enable.

VSBC writes only the low SEW-bit difference; it does not write a borrow mask. Use VMSBC.

VSBC cannot encode vd as v0 because v0 is fixed as borrow-in input.

FAQ

Is v0 an execution mask in VSBC.VXM?