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VSBC.VVM

RISC-V VSBC.VVM Instruction Details

Q: Is v0 an execution mask in VSBC.VVM?

No. The corresponding v0 bit is borrow-in arithmetic input.

Q: What result does VSBC.VVM write?

It writes the low SEW-bit difference; borrow-out is generated by VMSBC.

Instruction ManualOPIVV (OP-V)

VSBC uses the corresponding v0 bit as borrow-in, computes each body element's low SEW-bit difference, and writes vd.

Instruction Syntax

vsbc.vvm vd, vs2, vs1, v0

Operand Breakdown

Syntax: vsbc.vvm vd, vs2, vs1, v0; fixed vm=0, vm=1 encodings are reserved. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=010010.

Every body element computes vs2[i]-vs1[i]-v0.mask[i], writing low SEW bits to vd. v0 is borrow-in, not an execution enable; VMSBC generates borrow-out.

Body is vstart≤i<vl; every body element executes and tails follow vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.

Same-width sources/destination may overlap; vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.

Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.

VVector IntegerCarry/Borrow

Related Search Terms

vsbc.vvm instruction RISC-V vsbc.vvm vsbc.vvm syntax vsbc.vvm encoding RVV vector subtract with borrow vector vector borrow v0 borrow-in

Instruction Behavior

VSBC.VVM is the RISC-V V extension vector-vector subtract with borrow instruction. For each body element within the current vl, it computes vs2 - the second source - v0[i] and writes the low SEW-bit difference to the ordinary vector destination vd. v0 is borrow-in arithmetic input, not an ordinary v0.t execution mask; generate borrow-out with VMSBC.

VSBC.VVM Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VSBC uses each v0 bit as borrow-in, performs SEW-width subtract-with-borrow, and writes the difference.

Instruction input

vsbc.vvm

vdUse v1-v31; v0 is reservedvs2Use v1-v31; v0 supplies EEW=1 borrow-invs1Use v1-v31; v0 supplies EEW=1 borrow-in

arithmetic input, not execution mask

Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. Fix VLEN=4096 and VLMAX=4096/16=256; equal-width sources/destination may overlap. Fix vm=0; vm=1 is reserved. v0 supplies borrow-in, every body element executes, and vd cannot be v0. When v0 supplies the EEW=1 mask/borrow bits it cannot also supply data. Enter nonnegative element bit patterns. VL=0 updates no destination bits. Only body is shown without definite inactive/tail values; teaching stages are not processor cycles.

Execution Context

VLSEWvs2 elementscomma-separatedvs1 elementscomma-separatedv0 borrow-in bitseach bit is a 0/1 arithmetic input

OP-V encodingvsbc.vvm

funct6

010010

vs2

01000

vs1

01100

funct3

000

00100

opcode

1010111

lane

0x0000

0x003b

0x004c

0x0003

0x006e

0x007f

0x0002

0x00a1

-bin

v12

0x0005

0x0016

0x001f

0x0008

0x0031

0x003a

0x0006

0x004c

bin

...

Current step

Show OP-V 32-bit encoding fields

vsbc.vvm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows OP-V field decode, subtract-with-borrow, v0 borrow-in, and vd writeback; teaching stages are not processor cycles.

Quick Understanding & Search Notes

VSBC is the data-result instruction for multiword subtraction: v0 supplies the input bit, vd stores the low SEW-bit result, and VMSBC generates the output bit.

OP-V encoding uses funct6=010010; this .vvm form uses funct3=000 and takes the second source from vs1.

VSBC.VVM uses the corresponding v0 mask bit as borrow-in; this is not ordinary v0.t masked execution.

Destination vd is an ordinary vector result; the integer result is truncated to SEW and the output bit is not written by this instruction.

The official V extension reserves encodings where VSBC has vd equal to v0.

vm is fixed at 0; vm=1 encodings are reserved. Every body element with vstart≤i<vl executes. Tails follow vta; vl=0 leaves vd unchanged.

v0 supplies the EEW=1 borrow input and cannot also supply SEW data; equal-width data sources/destination may overlap under the general rules.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Vector Execution Context

Syntax: vsbc.vvm vd, vs2, vs1, v0; fixed vm=0, vm=1 encodings are reserved. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=010010.

Every body element computes vs2[i]-vs1[i]-v0.mask[i], writing low SEW bits to vd. v0 is borrow-in, not an execution enable; VMSBC generates borrow-out.

Body is vstart≤i<vl; every body element executes and tails follow vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.

Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Multi-Precision Sub

Assume enabled V/VS, valid m1, supported SEW, VLEN=4096 and XLEN=64, vl=4, vstart=0 and initialized sources. SEW=8, v12=[0,10,255,7], v4=[0,3,255,8], v0.mask[0..3]=1010 → v8=[255,7,255,255]. v0 supplies borrow-in; every body element executes and tails follow vta. vl=0 leaves vd unchanged.

BigInt

Pre-Use Checklist

Syntax Check

Syntax: vsbc.vvm vd, vs2, vs1, v0; fixed vm=0, vm=1 encodings are reserved. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=010010.
Every body element computes vs2[i]-vs1[i]-v0.mask[i], writing low SEW bits to vd. v0 is borrow-in, not an execution enable; VMSBC generates borrow-out.

Semantic Check

Body is vstart≤i<vl; every body element executes and tails follow vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
Same-width sources/destination may overlap; vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.

Pitfalls / Common Confusions

In VSBC.VVM, v0 is borrow-in arithmetic input, not an ordinary masked-execution element enable.

VSBC writes only the low SEW-bit difference; it does not write a borrow mask. Use VMSBC.

VSBC cannot encode vd as v0 because v0 is fixed as borrow-in input.

FAQ

Is v0 an execution mask in VSBC.VVM?