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VSBC.VVM

RISC-V VSBC.VVM Instruction Details

Instruction ManualR-type

VSBC uses the corresponding v0 bit as borrow-in, computes each body element's low SEW-bit difference, and writes vd.

Instruction Syntax

vsbc.vvm vd, vs2, vs1, v0

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector IntegerCarry/Borrow

Related Search Terms

vsbc.vvm instruction RISC-V vsbc.vvm vsbc.vvm syntax vsbc.vvm encoding RVV vector subtract with borrow vector vector borrow v0 borrow-in

Instruction Behavior

VSBC.VVM is the RISC-V V extension vector-vector subtract with borrow instruction. For each body element within the current vl, it computes vs2 - the second source - v0[i] and writes the low SEW-bit difference to the ordinary vector destination vd. v0 is borrow-in arithmetic input, not an ordinary v0.t execution mask; generate borrow-out with VMSBC.

VSBC.VVM Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VSBC uses each v0 bit as borrow-in, performs SEW-width subtract-with-borrow, and writes the difference.

Instruction input

vsbc.vvm

vdUse v1-v31; v0 is reservedvs2Use v0-v31vs1Use v0-v31

arithmetic input, not execution mask

VLSEWvs2 elementscomma-separatedvs1 elementscomma-separatedv0 borrow-in bitseach bit is a 0/1 arithmetic input

OP-V encodingvsbc.vvm

funct6

010010

vs2

01000

vs1

01100

funct3

000

00100

opcode

1010111

lane

0x0000

0x003b

0x004c

0x0003

0x006e

0x007f

0x0002

0x00a1

-bin

v12

0x0005

0x0016

0x001f

0x0008

0x0031

0x003a

0x0006

0x004c

bin

...

Current step

Show OP-V 32-bit encoding fields

vsbc.vvm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer subtract-with-borrow, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VSBC is the data-result instruction for multiword subtraction: v0 supplies the input bit, vd stores the low SEW-bit result, and VMSBC generates the output bit.

OP-V encoding uses funct6=010010; this .vvm form uses funct3=000 and takes the second source from vs1.

VSBC.VVM uses the corresponding v0 mask bit as borrow-in; this is not ordinary v0.t masked execution.

Destination vd is an ordinary vector result; the integer result is truncated to SEW and the output bit is not written by this instruction.

The official V extension reserves encodings where VSBC has vd equal to v0.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VSBC.VVM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Multi-Precision Sub

Understand this scenario with real code like «vsbc.vvm v8, v12, v4, v0».

BigInt

Understand this scenario with real code like «vsbc.vvm v8, v12, v4, v0».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

In VSBC.VVM, v0 is borrow-in arithmetic input, not an ordinary masked-execution element enable.

VSBC writes only the low SEW-bit difference; it does not write a borrow mask. Use VMSBC.

VSBC cannot encode vd as v0 because v0 is fixed as borrow-in input.

FAQ

Is v0 an execution mask in VSBC.VVM?

No. The corresponding v0 bit is borrow-in arithmetic input.

What result does VSBC.VVM write?

It writes the low SEW-bit difference; borrow-out is generated by VMSBC.