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VMSBC.VVM

RISC-V VMSBC.VVM Instruction Details

Q: Is v0 an execution mask in VMSBC.VVM?

No. The corresponding v0 bit is borrow-in arithmetic input.

Q: What result does VMSBC.VVM write?

It writes one destination mask bit for borrow-out.

Instruction ManualV-type

VMSBC computes each body element's borrow-out and writes the Boolean result to the destination mask register.

Instruction Syntax

vmsbc.vvm vd, vs2, vs1, v0

Operand Breakdown

Compute vs2[i]-vs1[i]-v0.mask[i] from unsigned SEW source bits; vd.mask[i]=1 exactly when the pre-truncation difference is negative. Fixed vm=0 uses v0 as borrow-in; every body element executes.

32-bit OP-V: opcode=1010111, funct6=010011, funct3=000. The destination is one mask register: bit i corresponds to element i, not an integer difference.

The mask destination may be v0. Different-EEW overlap must start at the source group's lowest register. With LMUL=m1, vd may equal a data source. With borrow-in, v0 cannot also supply SEW data.

Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Every body element writes a mask bit; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.

VVector IntegerCarry/Borrow

Related Search Terms

vmsbc.vvm instruction RISC-V vmsbc.vvm vmsbc.vvm syntax vmsbc.vvm encoding RVV vector subtract borrow-out vector vector borrow v0 borrow-in

Instruction Behavior

VMSBC.VVM computes vs2[i] - vs1[i] - v0.mask[i] from unsigned SEW source bit patterns for each body element. vd.mask[i] is 1 exactly when the difference before truncation is negative. Fixed vm=0 uses v0 as borrow-in, not an execution mask. Every body element executes; mask tails are always agnostic.

VMSBC.VVM Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMSBC uses each v0 bit as borrow-in and writes each borrow-out as a destination mask bit.

Instruction input

vmsbc.vvm

vdDestination mask register v0-v31vs2Use v1-v31; v0 supplies the EEW=1 mask/carryvs1Use v1-v31; v0 supplies the EEW=1 mask/carry

arithmetic input, not execution mask

Require valid vtype, enabled VS, and supported SEW; VL=0 updates no destination, including tails. VMSBC writes one mask bit per body element; tails are always agnostic. With m1, vd may equal a data source or v0. With borrow-in, v0 cannot also be a SEW data source.

Execution Context

VLSEWvs2 elementscomma-separatedvs1 elementscomma-separatedv0 borrow-in bitseach bit is a 0/1 arithmetic input

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvmsbc.vvm

funct6

010011

vs2

01000

vs1

01100

funct3

000

00100

opcode

1010111

lane

0x0000

0x003b

0x004c

0x0003

0x006e

0x007f

0x0002

0x00a1

-bin

v12

0x0005

0x0016

0x001f

0x0008

0x0031

0x003a

0x0006

0x004c

bin

v4.mask

...

Current step

Show OP-V 32-bit encoding fields

vmsbc.vvm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer borrow-out generation, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMSBC.VVM generates a borrow mask: vd.mask[i]=(unsigned(vs2[i])-unsigned(vs1[i])-v0.mask[i]<0).

OP-V encoding uses funct6=010011; this .vvm form uses funct3=000 and takes the second source from vs1.

VMSBC.VVM uses the corresponding v0 mask bit as borrow-in; this is not ordinary v0.t masked execution.

Destination vd is a mask result, one bit per body element.

VMSBC pairs with VSBC for multiword subtraction chains.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — V 1.0

Vector Execution Context

Compute vs2[i]-vs1[i]-v0.mask[i] from unsigned SEW source bits; vd.mask[i]=1 exactly when the pre-truncation difference is negative. Fixed vm=0 uses v0 as borrow-in; every body element executes.

32-bit OP-V: opcode=1010111, funct6=010011, funct3=000. The destination is one mask register: bit i corresponds to element i, not an integer difference.

The mask destination may be v0. Different-EEW overlap must start at the source group's lowest register. With LMUL=m1, vd may equal a data source. With borrow-in, v0 cannot also supply SEW data.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Multi-Precision Sub

Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v2=[0,7,0xffffffff,4], v3=[1,7,0,3], v0.mask=[0,1,0,1] → v1.mask[0..3]=[1,1,0,0]. Only borrow bits are written; mask tails are always agnostic.

BigInt

Pre-Use Checklist

Syntax Check

Compute vs2[i]-vs1[i]-v0.mask[i] from unsigned SEW source bits; vd.mask[i]=1 exactly when the pre-truncation difference is negative. Fixed vm=0 uses v0 as borrow-in; every body element executes.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=000. The destination is one mask register: bit i corresponds to element i, not an integer difference.

Semantic Check

The mask destination may be v0. Different-EEW overlap must start at the source group's lowest register. With LMUL=m1, vd may equal a data source. With borrow-in, v0 cannot also supply SEW data.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Every body element writes a mask bit; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.

Pitfalls / Common Confusions

In VMSBC.VVM, v0 is borrow-in arithmetic input, not an ordinary masked-execution element enable.

VMSBC writes destination mask bits, not ordinary SEW-width vector elements.

Each VMSBC mask result is a one-bit predicate, not a SEW-width integer value.

The destination is not a SEW-width difference; borrow follows unsigned-source subtraction before truncation, not signed overflow.

Body is vstart≤i<vl; prestart is unchanged and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails.

Require V 1.0, valid vtype, supported SEW, and enabled VS. The mask destination may be v0; source/destination overlap follows EEW/EMUL rules and may use the same register with LMUL=m1. With borrow-in, v0 cannot also supply SEW data.