Does VMSBC.VX write the add/subtract result?
No. It writes only borrow mask bits; data differences come from instructions such as VSBC.
VMSBC.VX
RISC-V VMSBC.VX Instruction Details
Instruction ManualOPIVXCompute element-wise subtract borrow-out and write the Boolean result to mask destination vd.
Instruction Syntax
vmsbc.vx vd, vs2, rs1
Operand Breakdown
Syntax: vmsbc.vx vd, vs2, rs1; vd is one mask register, vs2 is a SEW data source, and rs1 selects an integer scalar.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX). Fixed vm=1.
Compute unsigned vs2[i]-scalar; write 1 iff the pre-truncation difference is negative. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends. There is no borrow-in.
The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. An explicit vs2=v0 still reads data.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Every body element writes borrow-out; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
VVector IntegerCarry/Borrow
Instruction Behavior
VMSBC.VX is a RISC-V V-extension vector-scalar subtract borrow-out instruction. Each body element subtracts the SEW-width value of x[rs1] from unsigned vs2[i]. vd.mask[i] is 1 iff the difference before truncation is negative, otherwise 0. It writes borrow bits, not integer differences. Fixed vm=1 has no borrow-in or ordinary execution-mask operand.
VMSBC.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows non-m VMSBC processing every body element with vm=1, no borrow-in, and one borrow-out mask bit per element.
Instruction input
vmsbc.vx
vm
1
fixed unmasked encoding, not a syntax operandRequire valid vtype, enabled VS, and supported SEW; VL=0 updates no destination, including tails. VMSBC writes one mask bit per body element; tails are always agnostic. With m1, vd may equal a data source or v0. With borrow-in, v0 cannot also be a SEW data source.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMSBC.VX fixes vm=1 with no v0 borrow-in; when v0 is specified as a SEW data source, its data is still read. Each body element produces one destination-mask bit.
OP-V encodingvmsbc.vx
funct6
010011
vm
1
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
-
-
-
-
-
-
-
-
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmsbc.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer borrow-out generation, fixed vm=1 with no borrow-in, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSBC.VX generates only borrow bits: vd.mask[i] = (unsigned(vs2[i]) - unsigned(scalar) < 0).
OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX), vm=1.
Use low SEW bits of x[rs1] when XLEN>SEW; sign-extend when XLEN<SEW. Interpret the resulting bits as unsigned.
vd has one bit per element. Tails are always agnostic; VL=0 updates nothing, including tails.
With LMUL=m1, vd may equal a data source or v0. An explicit vs2=v0 still reads v0 as data.
Vector Execution Context
Syntax: vmsbc.vx vd, vs2, rs1; vd is one mask register, vs2 is a SEW data source, and rs1 selects an integer scalar.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX). Fixed vm=1.
Compute unsigned vs2[i]-scalar; write 1 iff the pre-truncation difference is negative. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends. There is no borrow-in.
The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. An explicit vs2=v0 still reads data.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Every body element writes borrow-out; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Common Usage Scenarios
Multi-Precision Sub
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; The example is unmasked. v2=[0,7,0xffffffff,4], x11=7 → v1.mask[0..3]=[1,0,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
BigInt
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; The example is unmasked. v2=[0,7,0xffffffff,4], x11=7 → v1.mask[0..3]=[1,0,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsbc.vx vd, vs2, rs1; vd is one mask register, vs2 is a SEW data source, and rs1 selects an integer scalar.
- 32-bit OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX). Fixed vm=1.
Semantic Check
- Compute unsigned vs2[i]-scalar; write 1 iff the pre-truncation difference is negative. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends. There is no borrow-in.
- The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. An explicit vs2=v0 still reads data.
- Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Every body element writes borrow-out; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Pitfalls / Common Confusions
Borrow tests whether the unsigned difference before truncation is negative, not the sign bit after truncation.
The non-m form fixes vm=1 and reads no v0 borrow-in.
The destination has one mask bit per element; tails are not guaranteed preserved, while VL=0 leaves the destination unchanged.