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VMSBC.VX

RISC-V VMSBC.VX Instruction Details

Instruction ManualOPIVX

Compute element-wise subtract borrow-out and write the Boolean result to mask destination vd.

Instruction Syntax

vmsbc.vx vd, vs2, rs1

Operand Breakdown

vd: mask destination register, with one Boolean result bit per element.

vs2/vs1 or scalar source: compared at the current SEW.

vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.

VVector IntegerCarry/Borrow

Related Search Terms

VMSBC.VX instruction RISC-V VMSBC.VX vmsbc.vx syntax vmsbc.vx RVV borrow out mask result

Instruction Behavior

VMSBC.VX is a RISC-V V vector subtract borrow-out instruction. It does not write the integer sum or difference; it writes each element's borrow-out as a destination mask bit. The form without the m suffix has no borrow input and no ordinary execution-mask operand. The destination is a mask register, not an ordinary SEW-width integer result.

VMSBC.VX Decode And Execute Animation

Instruction input

vmsbc.vx

vdDestination mask register v0-v31vs2Use v0-v31rs1Use x0-x31 or ABI name

fixed unmasked encoding, not a syntax operand

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rules

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. VMSBC.VX fixes vm=1, reads no v0 input, and produces one destination-mask bit for each body element.

OP-V encodingvmsbc.vx

funct6

010011

vs2

01000

rs1

01011

funct3

100

00100

opcode

1010111

lane

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

x11

0x0013

active

v4.mask

...

Current step

Show OP-V 32-bit encoding fields

vmsbc.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer , mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMSBC.VX generates a borrow mask; in m forms, v0 is borrow-in, not an ordinary execution mask.

Destination vd holds a one-bit mask result, one bit per element.

Forms without the m suffix do not read v0 as carry/borrow input.

Pair with VADC/VSBC for multiword add/subtract.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMSBC.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Multi-Precision Sub

Understand this scenario with real code like «vmsbc.vx v1, v2, a1».

BigInt

Understand this scenario with real code like «vmsbc.vx v1, v2, a1».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPIVX.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Borrow=1 if pre-truncation diff negative

No borrow-in in the non-m form

FAQ

Does VMSBC.VX write the add/subtract result?

No. It writes only borrow mask bits; data differences come from instructions such as VSBC.