Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMSBC.VV
RISC-V VMSBC.VV Instruction Details
Instruction ManualV-typeCompute element-wise subtract borrow-out and write the Boolean result to mask destination vd.
Instruction Syntax
vmsbc.vv vd, vs2, vs1
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerCarry/Borrow
Instruction Behavior
VMSBC.VV is the RISC-V V vector-vector subtract borrow-out instruction. It does not write a SEW-width integer difference; it writes one destination mask bit when an element's difference is negative before truncation. The non-m form fixes vm=1, reads no v0 borrow-in, and has no ordinary execution-mask operand, so every body element executes. Destination vd is a mask register, not an ordinary SEW-width integer result.
VMSBC.VV Decode And Execute Animation
Instruction input
vmsbc.vv
vm
1
fixed unmasked encoding, not a syntax operandThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. VMSBC.VV fixes vm=1, reads no v0 input, and produces one destination-mask bit for each body element.
OP-V encodingvmsbc.vv
funct6
010011
vm
1
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
-
-
-
-
-
-
-
-
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmsbc.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer , mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSBC.VV generates a borrow mask; in m forms, v0 is the carry/borrow input, not an ordinary execution mask.
Destination vd holds a one-bit mask result, one bit per element.
Forms without the m suffix do not read v0 as carry/borrow input.
Pair with VADC/VSBC for multiword add/subtract.
Vector Execution Context
When reading VMSBC.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Multi-Precision Sub
Understand this scenario with real code like «vmsbc.vv v1, v2, v3».
BigInt
Understand this scenario with real code like «vmsbc.vv v1, v2, v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Borrow-out is 1 if the difference before truncation is negative
The non-m form fixes vm=1 and reads no v0 borrow-in
FAQ
Does VMSBC.VV write the add/subtract result?
No. It writes only borrow-out mask bits; an integer difference is produced by a data instruction such as VSBC.