Does VMSBC.VV write the add/subtract result?
No. It writes only borrow-out mask bits; an integer difference is produced by a data instruction such as VSBC.
VMSBC.VV
RISC-V VMSBC.VV Instruction Details
Instruction ManualV-typeCompute element-wise subtract borrow-out and write the Boolean result to mask destination vd.
Instruction Syntax
vmsbc.vv vd, vs2, vs1
Operand Breakdown
Compute vs2[i]-vs1[i] from unsigned SEW source bits; vd.mask[i]=1 exactly when the pre-truncation difference is negative. Fixed vm=1 has no borrow-in; every body element executes.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=000. The destination is one mask register: bit i corresponds to element i, not an integer difference.
The mask destination may be v0. Different-EEW overlap must start at the source group's lowest register. With LMUL=m1, vd may equal a data source. With borrow-in, v0 cannot also supply SEW data.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Every body element writes a mask bit; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
VVector IntegerCarry/Borrow
Instruction Behavior
VMSBC.VV computes vs2[i] - vs1[i] from unsigned SEW source bit patterns for each body element. vd.mask[i] is 1 exactly when the difference before truncation is negative. Fixed vm=1 reads no v0 borrow-in and has no execution-mask operand. Every body element executes; mask tails are always agnostic.
VMSBC.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows non-m VMSBC processing every body element with vm=1, no borrow-in, and one borrow-out mask bit per element.
Instruction input
vmsbc.vv
vm
1
fixed unmasked encoding, not a syntax operandRequire valid vtype, enabled VS, and supported SEW; VL=0 updates no destination, including tails. VMSBC writes one mask bit per body element; tails are always agnostic. With m1, vd may equal a data source or v0. With borrow-in, v0 cannot also be a SEW data source.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMSBC.VV fixes vm=1 with no v0 borrow-in; when v0 is specified as a SEW data source, its data is still read. Each body element produces one destination-mask bit.
OP-V encodingvmsbc.vv
funct6
010011
vm
1
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
-
-
-
-
-
-
-
-
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmsbc.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer borrow-out generation, fixed vm=1 with no borrow-in, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSBC.VV generates a borrow mask: vd.mask[i]=(unsigned(vs2[i])-unsigned(vs1[i])<0).
Destination vd holds a one-bit mask result, one bit per element.
Forms without the m suffix do not read v0 as carry/borrow input.
VMSBC pairs with VSBC for multiword subtraction; preserve the same inputs when computing borrow and difference.
Vector Execution Context
Compute vs2[i]-vs1[i] from unsigned SEW source bits; vd.mask[i]=1 exactly when the pre-truncation difference is negative. Fixed vm=1 has no borrow-in; every body element executes.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=000. The destination is one mask register: bit i corresponds to element i, not an integer difference.
The mask destination may be v0. Different-EEW overlap must start at the source group's lowest register. With LMUL=m1, vd may equal a data source. With borrow-in, v0 cannot also supply SEW data.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Every body element writes a mask bit; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Common Usage Scenarios
Multi-Precision Sub
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v2=[0,7,0xffffffff,4], v3=[1,7,0,3] → v1.mask[0..3]=[1,0,0,0]. Only borrow bits are written; mask tails are always agnostic.
BigInt
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v2=[0,7,0xffffffff,4], v3=[1,7,0,3] → v1.mask[0..3]=[1,0,0,0]. Only borrow bits are written; mask tails are always agnostic.
Pre-Use Checklist
Syntax Check
- Compute vs2[i]-vs1[i] from unsigned SEW source bits; vd.mask[i]=1 exactly when the pre-truncation difference is negative. Fixed vm=1 has no borrow-in; every body element executes.
- 32-bit OP-V: opcode=1010111, funct6=010011, funct3=000. The destination is one mask register: bit i corresponds to element i, not an integer difference.
Semantic Check
- The mask destination may be v0. Different-EEW overlap must start at the source group's lowest register. With LMUL=m1, vd may equal a data source. With borrow-in, v0 cannot also supply SEW data.
- Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Every body element writes a mask bit; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Pitfalls / Common Confusions
Borrow-out is 1 if the difference before truncation is negative
The non-m form fixes vm=1 and reads no v0 borrow-in
The destination is not a SEW-width difference; borrow follows unsigned-source subtraction before truncation, not signed overflow.
Body is vstart≤i<vl; prestart is unchanged and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination, including tails.
Require V 1.0, valid vtype, supported SEW, and enabled VS. The mask destination may be v0; source/destination overlap follows EEW/EMUL rules and may use the same register with LMUL=m1. With borrow-in, v0 cannot also supply SEW data.