Can VAESDF.VS always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
VAESDF.VS
RISC-V VAESDF.VS Instruction Details
Instruction ManualR-typeVector AES final-round decryption using one scalar 128-bit round-key element group from vs2 for all state groups.
Instruction Syntax
vaesdf.vs vd, vs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvknedVector CryptoAES
Instruction Behavior
vaesdf.vs performs AES final-round decryption. Each 128-bit element group in vd is transformed using InvSubBytes+InvShiftRows and XORed with the scalar 128-bit round-key element group from vs2; the new state is written back to vd. SEW must be 32.
Quick Understanding & Search Notes
VAESDF.VS is a Zvkned vector instruction for vector AES final-round decryption. This page is checked against the official vector crypto extension and V-extension execution model.
Performs AES final-round decryption: InvShiftRows and InvSubBytes followed by XOR with the round key; SEW must be 32 and the element group is 128 bits.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vaesdf.vs vd, vs2».
Vector Acceleration
Understand this scenario with real code like «vaesdf.vs vd, vs2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
No vm operand; this element-group crypto instruction is not maskable.
The .vs scalar operand is an element group in vector register vs2, not a GPR or FP register.
For .vs, vd must not overlap the vs2 scalar element group.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
FAQ
What determines the element width for VAESDF.VS?
This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.