RISC-V VAESKF1.VI Instruction Details

Instruction ManualI-type

Vector AES-128 forward key-schedule step selected by uimm; SEW=32, no vm operand.

Instruction Syntax

vaeskf1.vi vd, vs2, uimm

Operand Breakdown

Destination rd: general-purpose register receiving the result.

Source rs1: register holding the first operand.

Immediate imm: 12-bit signed value, sign-extended before operation with rs1.

ZvknedVector CryptoAES

Related Search Terms

vaeskf1.vi instruction RISC-V vaeskf1.vi vaeskf1.vi syntax vaeskf1.vi encoding Zvkned vector AES-128 forward key schedule

Instruction Behavior

vaeskf1.vi is the Zvkned AES-128 forward key-schedule instruction. It reads the current round key from 128-bit element groups in vs2, uses the uimm-selected round number to generate the next AES-128 round key, and writes it to vd. SEW must be 32.

Quick Understanding & Search Notes

VAESKF1.VI is a Zvkned vector instruction for vector AES-128 forward key schedule. This page is checked against the official vector crypto extension and V-extension execution model.

Generates the next AES-128 round key from the current 128-bit round-key element group; uimm[3:0] is the round number with official out-of-range mapping.

This element-group crypto instruction has no vm mask operand and executes at element-group granularity.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.

RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vaeskf1.vi vd, vs2, uimm».

Vector Acceleration

Understand this scenario with real code like «vaeskf1.vi vd, vs2, uimm».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is I-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No vm operand; this key-schedule instruction is not maskable.

SEW must be 32 and each element group is 128 bits.

uimm selects the AES-128 round number/round constant; out-of-range immediates are projected as specified.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.

FAQ

Can VAESKF1.VI always use a v0.t mask?

No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.

What determines the element width for VAESKF1.VI?

This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.