Can VAESEM.VV always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
VAESEM.VV
RISC-V VAESEM.VV Instruction Details
Instruction ManualOP-VE (32-bit)Vector AES middle-round encryption: transform 128-bit state groups in vd with corresponding round-key groups from vs2.
Instruction Syntax
vaesem.vv vd, vs2
vd and vs2 select vector registers v0–v31; there is no immediate or third source operand. There is no v0.t mask operand; v0 is writable as ordinary data.
32-bit OP-VE: funct6=101000, vm=1, vs2[24:20], vs1=00010[19:15], funct3=010, vd[11:7], opcode=1110111.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. Apply SubBytes → ShiftRows → MixColumns to each active vd state group, then XOR its corresponding vs2 key group; equal-width source/destination overlap is allowed.
Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
ZvknedVector CryptoAES
Instruction Behavior
vaesem.vv performs AES middle-round encryption. Each 128-bit element group in vd is transformed using SubBytes+ShiftRows+MixColumns and XORed with the corresponding 128-bit round-key element group from vs2; the new state is written back to vd. SEW must be 32.
VAESEM.VV Decode And Execute Animation
This bounded model shows only official ISA-visible fields, state, and conditions; it does not model a complete cryptographic protocol or microarchitecture.
vaesem.vv
fixed 101000 / vm=1 / vs1=00010vs2=v16vs1=00010funct3=010vd=v8opcode=1110111
Execution Data Path
state -> SubBytes, ShiftRows, MixColumns, then AddRoundKey -> vd
result pending
Quick Understanding & Search Notes
Vector AES middle-round encryption: transform 128-bit state groups in vd with corresponding round-key groups from vs2.
Performs AES middle-round encryption including SubBytes, ShiftRows, MixColumns, and round-key XOR.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
Execution latency must not depend on operand data; reserved encodings do not promise a normal writeback or a particular exception.
Vector Execution Context
vd and vs2 select vector registers v0–v31; there is no immediate or third source operand. There is no v0.t mask operand; v0 is writable as ordinary data.
32-bit OP-VE: funct6=101000, vm=1, vs2[24:20], vs1=00010[19:15], funct3=010, vd[11:7], opcode=1110111.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. Apply SubBytes → ShiftRows → MixColumns to each active vd state group, then XOR its corresponding vs2 key group; equal-width source/destination overlap is allowed.
Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
Common Usage Scenarios
Crypto & Security
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero input groups in v8 and v16, the basic example's round number and this page's rules produce v8=0x63636363636363636363636363636363.
Vector Acceleration
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero input groups in v8 and v16, the basic example's round number and this page's rules produce v8=0x63636363636363636363636363636363.
Pre-Use Checklist
Syntax Check
- vd and vs2 select vector registers v0–v31; there is no immediate or third source operand. There is no v0.t mask operand; v0 is writable as ordinary data.
- 32-bit OP-VE: funct6=101000, vm=1, vs2[24:20], vs1=00010[19:15], funct3=010, vd[11:7], opcode=1110111.
Semantic Check
- Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. Apply SubBytes → ShiftRows → MixColumns to each active vd state group, then XOR its corresponding vs2 key group; equal-width source/destination overlap is allowed.
- Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
Pitfalls / Common Confusions
No vm operand; this element-group crypto instruction is not maskable.
SEW must be 32 and each element group is 128 bits.
vd is both input state and destination.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
FAQ
What determines the element width for VAESEM.VV?
Defined only for SEW=32, with EGW=128 and EGS=4. Other SEW values, or vl/vstart not divisible by 4, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0.