Can VAESEF.VV always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
VAESEF.VV
RISC-V VAESEF.VV Instruction Details
Instruction ManualOP-VE vector-vector formVector AES final-round encryption: transform 128-bit state groups in vd with corresponding round-key groups from vs2.
Instruction Syntax
vaesef.vv vd, vs2
vd supplies the old state and receives the new state; vs2 supplies round keys, both using vector registers v0–v31. There is no third source, immediate or v0.t mask operand; v0 is writable as data.
32-bit OP-VE: opcode=1110111, funct6=101000, vm=1, vs1=00011, funct3=010; vs1 is a fixed selector, not a source operand.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. SubBytes → ShiftRows → round-key XOR (no MixColumns); each active state group uses its corresponding vs2 round-key group; the same register may hold state and key.
Process groups vstart/4 through vl/4−1. Encodings with vl or vstart not a multiple of 4, or other SEW values, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Execution latency must not depend on operand data.
ZvknedVector CryptoAES
Instruction Behavior
vaesef.vv performs AES final-round encryption. Each 128-bit element group in vd undergoes SubBytes, then ShiftRows, then XOR with the corresponding 128-bit round-key element group from vs2; the new state is written back to vd. SEW must be 32.
VAESEF.VV Decode And Execute Animation
This bounded model shows only official ISA-visible fields, state, and conditions; it does not model a complete cryptographic protocol or microarchitecture.
vaesef.vv
fixed 101000 / vm=1 / vs1=00011vs2=v16vs1=00011funct3=010vd=v8opcode=1110111
Execution Data Path
state -> SubBytes, ShiftRows, then AddRoundKey -> vd
result pending
Quick Understanding & Search Notes
Vector AES final-round encryption: transform 128-bit state groups in vd with corresponding round-key groups from vs2.
Performs AES final-round encryption: SubBytes, then ShiftRows, followed by XOR with the round key; it does not include MixColumns.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; encodings with vl or vstart not a multiple of 4 are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even when vl=0.
Vector Execution Context
vd supplies the old state and receives the new state; vs2 supplies round keys, both using vector registers v0–v31. There is no third source, immediate or v0.t mask operand; v0 is writable as data.
32-bit OP-VE: opcode=1110111, funct6=101000, vm=1, vs1=00011, funct3=010; vs1 is a fixed selector, not a source operand.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. SubBytes → ShiftRows → round-key XOR (no MixColumns); each active state group uses its corresponding vs2 round-key group; the same register may hold state and key.
Process groups vstart/4 through vl/4−1. Encodings with vl or vstart not a multiple of 4, or other SEW values, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Execution latency must not depend on operand data.
Common Usage Scenarios
Crypto & Security
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero state in v8 and zero key in v16, this round function writes v8=0x63636363636363636363636363636363, updating this active group only.
Vector Acceleration
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero state in v8 and zero key in v16, this round function writes v8=0x63636363636363636363636363636363, updating this active group only.
Pre-Use Checklist
Syntax Check
- vd supplies the old state and receives the new state; vs2 supplies round keys, both using vector registers v0–v31. There is no third source, immediate or v0.t mask operand; v0 is writable as data.
- 32-bit OP-VE: opcode=1110111, funct6=101000, vm=1, vs1=00011, funct3=010; vs1 is a fixed selector, not a source operand.
Semantic Check
- Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. SubBytes → ShiftRows → round-key XOR (no MixColumns); each active state group uses its corresponding vs2 round-key group; the same register may hold state and key.
- Process groups vstart/4 through vl/4−1. Encodings with vl or vstart not a multiple of 4, or other SEW values, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Execution latency must not depend on operand data.
Pitfalls / Common Confusions
No vm operand; this element-group crypto instruction is not maskable.
SEW must be 32 and each element group is 128 bits.
vd is both input state and destination.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
FAQ
What determines the element width for VAESEF.VV?
This instruction fixes SEW=32 and executes on 128-bit element groups; encodings with other SEW values are reserved.