Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VAESEF.VV
RISC-V VAESEF.VV Instruction Details
Instruction ManualR-typeVector AES final-round encryption: transform 128-bit state groups in vd with corresponding round-key groups from vs2.
Instruction Syntax
vaesef.vv vd, vs2
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvknedVector CryptoAES
Instruction Behavior
vaesef.vv performs AES final-round encryption. Each 128-bit element group in vd is transformed using SubBytes+ShiftRows and XORed with the corresponding 128-bit round-key element group from vs2; the new state is written back to vd. SEW must be 32.
Quick Understanding & Search Notes
VAESEF.VV is a Zvkned vector instruction for vector AES final-round encryption. This page is checked against the official vector crypto extension and V-extension execution model.
Performs AES final-round encryption: ShiftRows and SubBytes followed by XOR with the round key; it does not include MixColumns.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
Vector Execution Context
When reading VAESEF.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vaesef.vv vd, vs2».
Vector Acceleration
Understand this scenario with real code like «vaesef.vv vd, vs2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
No vm operand; this element-group crypto instruction is not maskable.
SEW must be 32 and each element group is 128 bits.
vd is both input state and destination.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
FAQ
Can VAESEF.VV always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
What determines the element width for VAESEF.VV?
This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.