Can VAESDF.VV always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
VAESDF.VV
RISC-V VAESDF.VV Instruction Details
Instruction ManualOP-VE vector-vector formVector AES final-round decryption: transform 128-bit state groups in vd with corresponding round-key groups from vs2.
Instruction Syntax
vaesdf.vv vd, vs2
vd supplies the old state and receives the new state; vs2 supplies 128-bit round-key groups. Operands are vector registers, with no v0.t or integer scalar source.
32-bit OP-VE: opcode=1110111, funct6=101000, vm=1, vs1=00001, funct3=010; the vs1 field is not a source operand.
Requires Zvkned, SEW=32, EGW=128, EGS=4. Apply InvShiftRows, InvSubBytes, then XOR the corresponding vs2 element group; the final round has no InvMixColumns.
vl and vstart must be multiples of 4, otherwise the encoding is reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0; other SEW encodings are reserved.
ZvknedVector CryptoAES
Instruction Behavior
vaesdf.vv performs AES final-round decryption. Each 128-bit element group in vd is transformed by InvShiftRows followed by InvSubBytes, then XORed with the corresponding 128-bit round-key element group from vs2; the new state is written back to vd. SEW must be 32.
VAESDF.VV Decode And Execute Animation
This bounded model shows only official ISA-visible fields, state, and conditions; it does not model a complete cryptographic protocol or microarchitecture.
vaesdf.vv
fixed 101000 / vm=1 / vs1=00001vs2=v16vs1=00001funct3=010vd=v8opcode=1110111
Execution Data Path
state -> InvShiftRows, InvSubBytes, then AddRoundKey -> vd
result pending
Quick Understanding & Search Notes
VAESDF.VV applies InvShiftRows and InvSubBytes to 128-bit state groups in vd, then XORs the corresponding round-key group from vs2; SEW=32.
Performs AES final-round decryption: InvShiftRows and InvSubBytes followed by XOR with the round key; SEW must be 32 and the element group is 128 bits.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
Vector Execution Context
vd supplies the old state and receives the new state; vs2 supplies 128-bit round-key groups. Operands are vector registers, with no v0.t or integer scalar source.
32-bit OP-VE: opcode=1110111, funct6=101000, vm=1, vs1=00001, funct3=010; the vs1 field is not a source operand.
Requires Zvkned, SEW=32, EGW=128, EGS=4. Apply InvShiftRows, InvSubBytes, then XOR the corresponding vs2 element group; the final round has no InvMixColumns.
vl and vstart must be multiples of 4, otherwise the encoding is reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0; other SEW encodings are reserved.
Common Usage Scenarios
Crypto & Security
Zvkned, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, with zero state in v8 and zero key in v16: success writes v8=0x52525252525252525252525252525252.
Vector Acceleration
Zvkned, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, with zero state in v8 and zero key in v16: success writes v8=0x52525252525252525252525252525252.
Pre-Use Checklist
Syntax Check
- vd supplies the old state and receives the new state; vs2 supplies 128-bit round-key groups. Operands are vector registers, with no v0.t or integer scalar source.
- 32-bit OP-VE: opcode=1110111, funct6=101000, vm=1, vs1=00001, funct3=010; the vs1 field is not a source operand.
Semantic Check
- Requires Zvkned, SEW=32, EGW=128, EGS=4. Apply InvShiftRows, InvSubBytes, then XOR the corresponding vs2 element group; the final round has no InvMixColumns.
- vl and vstart must be multiples of 4, otherwise the encoding is reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0; other SEW encodings are reserved.
Pitfalls / Common Confusions
No vm operand; this element-group crypto instruction is not maskable.
SEW must be 32 and each element group is 128 bits.
vd is both input state and destination.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
FAQ
What determines the element width for VAESDF.VV?
This instruction fixes SEW=32 and executes on 128-bit element groups; encodings with other SEW values are reserved.