Can VAESKF2.VI always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
VAESKF2.VI
RISC-V VAESKF2.VI Instruction Details
Instruction ManualOP-VE (32-bit)Vector AES-256 forward key-schedule step selected by uimm; SEW=32, no vm operand.
Instruction Syntax
vaeskf2.vi vd, vs2, uimm
vd and vs2 select vector registers v0–v31; uimm is a five-bit unsigned immediate, 0–31. There is no v0.t mask operand; v0 is writable as ordinary data.
32-bit OP-VE: funct6=101010, vm=1, vs2[24:20], uimm[4:0][19:15], funct3=010, vd[11:7], opcode=1110111.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. vs2 provides the current key, old vd the previous key, and vd receives the next key. Rounds 2–14: ignore uimm[4]; low-four-bit 0/1/15 map to 8/9/7.
Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
ZvknedVector CryptoAES
Instruction Encoding
31..26
funct6=101010
25
vm=1
24..20
vs2
19..15
uimm[4:0]
14..12
010
11..7
vd
6..0
1110111
VAESKF2.VI uses opcode 1110111 (0x77), funct3 010. 32-bit OP-VE: funct6=101010, vm=1, vs2[24:20], uimm[4:0][19:15], funct3=010, vd[11:7], opcode=1110111.
Format: OP-VE (funct6=101010, vm=1, uimm[4:0])
opcode: 1110111 (0x77)
funct3: 010 (0x2)
Instruction Behavior
vaeskf2.vi is the Zvkned AES-256 forward key-schedule instruction. It reads the current AES-256 round-key element group from vs2 and combines it with the previous round-key state in vd and the uimm-selected round number to generate the next round key, writing the result to vd. SEW must be 32. It is only for AES-256 forward key scheduling.
Quick Understanding & Search Notes
Vector AES-256 forward key-schedule step selected by uimm; SEW=32, no vm operand.
Generates the next AES-256 forward key-schedule material using vs2 and the old vd state.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
Execution latency must not depend on operand data; reserved encodings do not promise a normal writeback or a particular exception.
For odd effective rounds, apply only SubWord to the high vs2 word. For even rounds, apply RotWord, SubWord and XOR Rcon[(rnd>>1)−1]. XOR the low old-vd word to form w0, then chain XORs with the remaining old-vd words.
Vector Execution Context
vd and vs2 select vector registers v0–v31; uimm is a five-bit unsigned immediate, 0–31. There is no v0.t mask operand; v0 is writable as ordinary data.
32-bit OP-VE: funct6=101010, vm=1, vs2[24:20], uimm[4:0][19:15], funct3=010, vd[11:7], opcode=1110111.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. vs2 provides the current key, old vd the previous key, and vd receives the next key. Rounds 2–14: ignore uimm[4]; low-four-bit 0/1/15 map to 8/9/7.
Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
Common Usage Scenarios
Crypto & Security
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero input groups in v8 and v16, the basic example's round number and this page's rules produce v8=0x63636362636363626363636263636362.
Vector Acceleration
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero input groups in v8 and v16, the basic example's round number and this page's rules produce v8=0x63636362636363626363636263636362.
Pre-Use Checklist
Syntax Check
- vd and vs2 select vector registers v0–v31; uimm is a five-bit unsigned immediate, 0–31. There is no v0.t mask operand; v0 is writable as ordinary data.
- 32-bit OP-VE: funct6=101010, vm=1, vs2[24:20], uimm[4:0][19:15], funct3=010, vd[11:7], opcode=1110111.
Semantic Check
- Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. vs2 provides the current key, old vd the previous key, and vd receives the next key. Rounds 2–14: ignore uimm[4]; low-four-bit 0/1/15 map to 8/9/7.
- Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
Pitfalls / Common Confusions
No vm operand; this key-schedule instruction is not maskable.
SEW must be 32 and each element group is 128 bits.
Used for AES-256 forward key schedule; do not describe it as another AES round transform.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
uimm is a five-bit unsigned immediate, 0–31; uimm[4] is ignored. Low-four-bit values 0, 1 or 15 invert bit3: 0→8, 1→9 and 15→7, giving rounds 2–14.
FAQ
What determines the element width for VAESKF2.VI?
Defined only for SEW=32, with EGW=128 and EGS=4. Other SEW values, or vl/vstart not divisible by 4, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0.
Are all five-bit uimm values defined?
uimm is a five-bit unsigned immediate, 0–31; uimm[4] is ignored. Low-four-bit values 0, 1 or 15 invert bit3: 0→8, 1→9 and 15→7, giving rounds 2–14.