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VAESZ.VS

RISC-V VAESZ.VS Instruction Details

Instruction ManualR-type

Vector AES round-zero XOR: XOR each 128-bit state group in vd with the scalar round-key element group from vs2.

Instruction Syntax

vaesz.vs vd, vs2

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

ZvknedVector CryptoAES

Related Search Terms

vaesz.vs instruction RISC-V vaesz.vs vaesz.vs syntax vaesz.vs encoding Zvkned vector AES round-zero XOR

Instruction Behavior

vaesz.vs performs AES round-zero encryption/decryption. It XORs each 128-bit state element group in vd with the scalar 128-bit round-key element group from vs2 and writes the new state to vd. SEW must be 32; there is only a .vs form.

Quick Understanding & Search Notes

VAESZ.VS is a Zvkned vector instruction for vector AES round-zero XOR. This page is checked against the official vector crypto extension and V-extension execution model.

XORs each 128-bit state element group in vd with the scalar 128-bit round-key element group from vs2; only the .vs form exists.

This element-group crypto instruction has no vm mask operand and executes at element-group granularity.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.

RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VAESZ.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vaesz.vs vd, vs2».

Vector Acceleration

Understand this scenario with real code like «vaesz.vs vd, vs2».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No vm operand; this element-group crypto instruction is not maskable.

The scalar round key is a 128-bit element group in vs2, not rs1.

vd must not overlap the vs2 scalar element group.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.

FAQ

Can VAESZ.VS always use a v0.t mask?

No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.

What determines the element width for VAESZ.VS?

This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.