RISC-V VAESZ.VS Instruction Details

Instruction ManualR-type

Vector AES round-zero XOR: XOR each 128-bit state group in vd with the scalar round-key element group from vs2.

Instruction Syntax

vaesz.vs vd, vs2

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

ZvknedVector CryptoAES

Related Search Terms

vaesz.vs instruction RISC-V vaesz.vs vaesz.vs syntax vaesz.vs encoding Zvkned vector AES round-zero XOR

Instruction Behavior

vaesz.vs performs AES round-zero encryption/decryption. It XORs each 128-bit state element group in vd with the scalar 128-bit round-key element group from vs2 and writes the new state to vd. SEW must be 32; there is only a .vs form.

Quick Understanding & Search Notes

VAESZ.VS is a Zvkned vector instruction for vector AES round-zero XOR. This page is checked against the official vector crypto extension and V-extension execution model.

XORs each 128-bit state element group in vd with the scalar 128-bit round-key element group from vs2; only the .vs form exists.

This element-group crypto instruction has no vm mask operand and executes at element-group granularity.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.

RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vaesz.vs vd, vs2».

Vector Acceleration

Understand this scenario with real code like «vaesz.vs vd, vs2».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No vm operand; this element-group crypto instruction is not maskable.

The scalar round key is a 128-bit element group in vs2, not rs1.

vd must not overlap the vs2 scalar element group.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.

FAQ

Can VAESZ.VS always use a v0.t mask?

No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.

What determines the element width for VAESZ.VS?

This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.