Can VAESZ.VS always use a v0.t mask?
No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.
VAESZ.VS
RISC-V VAESZ.VS Instruction Details
Instruction ManualOP-VE (32-bit)Vector AES round-zero XOR: XOR each 128-bit state group in vd with the scalar round-key element group from vs2.
Instruction Syntax
vaesz.vs vd, vs2
vd and vs2 select vector registers v0–v31; there is no immediate or third source operand. There is no v0.t mask operand; v0 is writable as ordinary data.
32-bit OP-VE: funct6=101001, vm=1, vs2[24:20], vs1=00111[19:15], funct3=010, vd[11:7], opcode=1110111.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. XOR each active state group in vd with vs2 scalar element group 0; encodings where vd overlaps that scalar group are reserved.
Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
ZvknedVector CryptoAES
Instruction Encoding
31..26
funct6=101001
25
vm=1
24..20
vs2
19..15
00111
14..12
010
11..7
vd
6..0
1110111
VAESZ.VS uses opcode 1110111 (0x77), funct3 010. 32-bit OP-VE: funct6=101001, vm=1, vs2[24:20], vs1=00111[19:15], funct3=010, vd[11:7], opcode=1110111.
Format: OP-VE (funct6=101001, vm=1, vs1=00111)
opcode: 1110111 (0x77)
funct3: 010 (0x2)
Instruction Behavior
vaesz.vs performs AES round-zero encryption/decryption. It XORs each 128-bit state element group in vd with the scalar 128-bit round-key element group from vs2 and writes the new state to vd. SEW must be 32; there is only a .vs form.
Quick Understanding & Search Notes
Vector AES round-zero XOR: XOR each 128-bit state group in vd with the scalar round-key element group from vs2.
XORs each 128-bit state element group in vd with the scalar 128-bit round-key element group from vs2; only the .vs form exists.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
Execution latency must not depend on operand data; reserved encodings do not promise a normal writeback or a particular exception.
Vector Execution Context
vd and vs2 select vector registers v0–v31; there is no immediate or third source operand. There is no v0.t mask operand; v0 is writable as ordinary data.
32-bit OP-VE: funct6=101001, vm=1, vs2[24:20], vs1=00111[19:15], funct3=010, vd[11:7], opcode=1110111.
Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. XOR each active state group in vd with vs2 scalar element group 0; encodings where vd overlaps that scalar group are reserved.
Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
Common Usage Scenarios
Crypto & Security
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero input groups in v8 and v16, the basic example's round number and this page's rules produce v8=0x00000000000000000000000000000000.
Vector Acceleration
With Zvkned and vector state enabled, VLEN=128, LMUL=1, SEW=32, vl=4, vstart=0, and zero input groups in v8 and v16, the basic example's round number and this page's rules produce v8=0x00000000000000000000000000000000.
Pre-Use Checklist
Syntax Check
- vd and vs2 select vector registers v0–v31; there is no immediate or third source operand. There is no v0.t mask operand; v0 is writable as ordinary data.
- 32-bit OP-VE: funct6=101001, vm=1, vs2[24:20], vs1=00111[19:15], funct3=010, vd[11:7], opcode=1110111.
Semantic Check
- Requires enabled Zvkned and vector state, SEW=32, EGW=128, EGS=4. XOR each active state group in vd with vs2 scalar element group 0; encodings where vd overlaps that scalar group are reserved.
- Process groups vstart/4 through vl/4−1. Encodings with vl/vstart not divisible by 4, or SEW≠32, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0. Register groups follow V-extension alignment rules; execution latency must not depend on operand data.
Pitfalls / Common Confusions
No vm operand; this element-group crypto instruction is not maskable.
The scalar round key is a 128-bit element group in vs2, not rs1.
vd must not overlap the vs2 scalar element group.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must cover at least one 128-bit element group.
FAQ
What determines the element width for VAESZ.VS?
Defined only for SEW=32, with EGW=128 and EGS=4. Other SEW values, or vl/vstart not divisible by 4, are reserved. LMUL*VLEN<128 raises an illegal-instruction exception even if vl=0.