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VCLMULH.VX

RISC-V VCLMULH.VX Instruction Details

Instruction ManualR-type

Vector-scalar carry-less multiply high: GF(2) multiply with broadcast rs1, high SEW bits

Instruction Syntax

vclmulh.vx vd, vs2, rs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

ZvbcVector CryptoBit Manipulation

Related Search Terms

vclmulh.vx instruction RISC-V vclmulh.vx vclmulh.vx syntax vclmulh.vx encoding Zvbc vector-scalar carry-less multiply high

Instruction Behavior

vclmulh.vx is the Zvbc vector-scalar carry-less multiply high. Broadcasts rs1, performs GF(2) multiply with vs2[i], returning high SEW bits. SEW=64.

Quick Understanding & Search Notes

VCLMULH.VX is a Zvbc vector instruction for vector-scalar carry-less multiply high. This page is checked against the official vector crypto extension and V-extension execution model.

The scalar and each element are carry-less multiplied, returning high SEW bits; SEW=64.

It follows V-extension vl, vstart, vtype, and optional vm mask rules.

Zvbc vclmul/vclmulh are defined only for SEW=64.

RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VCLMULH.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vclmulh.vx vd, vs2, a1».

Vector Acceleration

Understand this scenario with real code like «vclmulh.vx vd, vs2, a1».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

SEW=64. Returns high 64 bits.

FAQ

Can VCLMULH.VX always use a v0.t mask?

It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.

What determines the element width for VCLMULH.VX?

The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.