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VGHSH.VV

RISC-V VGHSH.VV Instruction Details

Instruction ManualR-type

Vector GHASH add-multiply: update partial hash in vd using ciphertext vs1 and hash subkey vs2.

Instruction Syntax

vghsh.vv vd, vs2, vs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvkgVector CryptoGCM/GHASH
Related Search Terms
vghsh.vv instructionRISC-V vghsh.vvvghsh.vv syntaxvghsh.vv encodingZvkgvector GHASH add-multiply

Instruction Behavior

vghsh.vv performs a GHASH add-multiply over 128-bit element groups with SEW=32. It reads partial hash Y_i from vd, ciphertext X_i from vs1, hash subkey H from vs2, and writes updated partial hash Y_{i+1} to vd.

Quick Understanding & Search Notes

VGHSH.VV is a Zvkg vector instruction for vector GHASH add-multiply. This page is checked against the official vector crypto extension and V-extension execution model.

Performs the GHASH (Y_i + X_i) * H update over 128-bit element groups with SEW=32.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0RISC-V Unprivileged ISA Manual: V standard vector extension

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vghsh.vv vd, vs2, vs1».

Vector Acceleration

Understand this scenario with real code like «vghsh.vv vd, vs2, vs1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No vm operand; this element-group crypto instruction is not maskable.
Requires SEW=32, EGW=128. Operates on 128-bit group granularity.
GHASH uses a special polynomial in GF(2^128), not ordinary integer arithmetic.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must be at least 128.

FAQ

Can VGHSH.VV always use a v0.t mask?

No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.

What determines the element width for VGHSH.VV?

This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.