How does VCLMUL.VV use masking?
Append optional v0.t for vm=0; omit it for vm=1. vm is an encoding field, not an assembly register operand. Mask and register-group overlap constraints still apply.
VCLMUL.VV
RISC-V VCLMUL.VV Instruction Details
Instruction ManualV-typeCarry-less multiply low: GF(2) polynomial multiplication, low 64 bits; SEW=64 only.
Instruction Syntax
vclmul.vv vd, vs2, vs1[, v0.t]
vd, vs2 and vs1 select v0–v31. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
32-bit OP-V: funct6=001100, vm[25], vs2[24:20], vs1[19:15], funct3=010, vd[11:7], opcode=1010111.
Zvbc depends on Zve64x. Only SEW=64 is defined; other SEWs are reserved. Active elements perform GF(2) carry-less multiplication and return the low 64 bits of the 128-bit product.
Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
ZvbcVector CryptoBit Manipulation
Instruction Behavior
vclmul.vv performs GF(2) carry-less multiplication of vs2[i] and vs1[i], writing the low 64 bits to vd[i]. It is defined only for SEW=64.
VCLMUL.VV Decode & Execute Animation
This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.
Execution context: enable the listed extension and vector state, use a legal supported vtype, LMUL=1 and VLEN≥64×SEW. Only lane 0 is expanded; vl=32/64 does not replicate it to other elements. SEW=64 requires Zve64x. Nonzero vstart assumes implementation support; otherwise an illegal-instruction exception is permitted.
Bounded execution context
32-bit OP-V encoding fields
31..26
funct6
001100
25
vm
1
24..20
vs2
01000
19..15
vs1
01100
14..12
funct3
010
11..7
vd
00100
6..0
OP-V
1010111
Execution data path
funct6=001100, funct3=010, Zvbc
v4[0] <- pending
Quick Understanding & Search Notes
vclmul.vv is provided by Zvbc for carry-less multiply low. Only SEW=64 is defined.
vclmul.vv performs GF(2) carry-less multiplication of vs2[i] and vs1[i], writing the low 64 bits to vd[i]. It is defined only for SEW=64.
Process active elements where vstart≤i<vl and the mask enables execution. Prestart elements are undisturbed; masked-off and tail elements follow vma/vta, with agnostic values retained or set to all ones. vstart≥vl (including vl=0) leaves all destinations unchanged. Success resets vstart; implementations may reject nonzero vstart.
Same-width source/destination groups may overlap and read original source values; groups must follow LMUL alignment. A masked destination may not overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Vector Execution Context
vd, vs2 and vs1 select v0–v31. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
32-bit OP-V: funct6=001100, vm[25], vs2[24:20], vs1[19:15], funct3=010, vd[11:7], opcode=1010111.
Zvbc depends on Zve64x. Only SEW=64 is defined; other SEWs are reserved. Active elements perform GF(2) carry-less multiplication and return the low 64 bits of the 128-bit product.
Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
Common Usage Scenarios
Apply carry-less multiply low to active vector elements.
With the listed extension and vector state enabled, legal vtype, LMUL=1, VLEN≥128, vl=1, vstart=0 and no mask: SEW=64, v8[0]=0x3, v12[0]=0x3: 0x3 XOR (0x3 << 1) = 0x5, written to v4[0].
Pre-Use Checklist
Syntax Check
- vd, vs2 and vs1 select v0–v31. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
- 32-bit OP-V: funct6=001100, vm[25], vs2[24:20], vs1[19:15], funct3=010, vd[11:7], opcode=1010111.
Semantic Check
- Zvbc depends on Zve64x. Only SEW=64 is defined; other SEWs are reserved. Active elements perform GF(2) carry-less multiplication and return the low 64 bits of the 128-bit product.
- Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
- Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
Pitfalls / Common Confusions
Carry-less (GF(2) polynomial) multiply, not integer multiply.
Returns low SEW bits; high SEW bits use vclmulh. SEW=64.
FAQ
Which element widths does VCLMUL.VV support?
Only SEW=64; other SEW encodings are reserved. Zvbc depends on Zve64x.