Can VCLMULH.VV always use a v0.t mask?
It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.
VCLMULH.VV
RISC-V VCLMULH.VV Instruction Details
Instruction ManualR-typeVector carry-less multiply high: GF(2) polynomial multiply returning high SEW bits
Instruction Syntax
vclmulh.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvbcVector CryptoBit Manipulation
Instruction Behavior
vclmulh.vv is the Zvbc vector carry-less multiply high. Performs GF(2) polynomial multiply on vs1[i] and vs2[i], returning the high SEW bits. Paired with vclmul.vv for full 2*SEW product. SEW=64.
Quick Understanding & Search Notes
VCLMULH.VV is a Zvbc vector instruction for vector carry-less multiply high. This page is checked against the official vector crypto extension and V-extension execution model.
Returns the high SEW bits of the 2*SEW carry-less product; SEW=64.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Zvbc vclmul/vclmulh are defined only for SEW=64.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vclmulh.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vclmulh.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Returns high SEW bits; pair with vclmul.vv for full 128-bit product.
SEW=64. Used in GCM/GHASH authenticated encryption.
FAQ
What determines the element width for VCLMULH.VV?
The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.