Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VCLMULH.VV
RISC-V VCLMULH.VV Instruction Details
Instruction ManualR-typeVector carry-less multiply high: GF(2) polynomial multiply returning high SEW bits
Instruction Syntax
vclmulh.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvbcVector CryptoBit Manipulation
Instruction Behavior
vclmulh.vv is the Zvbc vector carry-less multiply high. Performs GF(2) polynomial multiply on vs1[i] and vs2[i], returning the high SEW bits. Paired with vclmul.vv for full 2*SEW product. SEW=64.
Quick Understanding & Search Notes
VCLMULH.VV is a Zvbc vector instruction for vector carry-less multiply high. This page is checked against the official vector crypto extension and V-extension execution model.
Returns the high SEW bits of the 2*SEW carry-less product; SEW=64.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Zvbc vclmul/vclmulh are defined only for SEW=64.
Vector Execution Context
When reading VCLMULH.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vclmulh.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vclmulh.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Returns high SEW bits; pair with vclmul.vv for full 128-bit product.
SEW=64. Used in GCM/GHASH authenticated encryption.
FAQ
Can VCLMULH.VV always use a v0.t mask?
It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.
What determines the element width for VCLMULH.VV?
The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.