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VGMUL.VV

RISC-V VGMUL.VV Instruction Details

Instruction ManualR-type

Vector GHASH multiply: multiply 128-bit element groups in vd by hash subkey groups in vs2.

Instruction Syntax

vgmul.vv vd, vs2

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

ZvkgVector CryptoGCM/GHASH

Related Search Terms

vgmul.vv instruction RISC-V vgmul.vv vgmul.vv syntax vgmul.vv encoding Zvkg vector GHASH field multiply

Instruction Behavior

vgmul.vv performs a GHASH field multiply over 128-bit element groups with SEW=32. It reads one operand from vd and the other from vs2, then writes the product back to vd.

Quick Understanding & Search Notes

VGMUL.VV is a Zvkg vector instruction for vector GHASH field multiply. This page is checked against the official vector crypto extension and V-extension execution model.

Performs GHASH GF(2^128) field multiplication over 128-bit element groups with SEW=32.

This element-group crypto instruction has no vm mask operand and executes at element-group granularity.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.

RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VGMUL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vgmul.vv vd, vs2».

Vector Acceleration

Understand this scenario with real code like «vgmul.vv vd, vs2».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No vm operand; this element-group crypto instruction is not maskable.

Requires SEW=32, EGW=128. Multiplication by GHASH subkey H.

SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must be at least 128.

FAQ

Can VGMUL.VV always use a v0.t mask?

No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.

What determines the element width for VGMUL.VV?

This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.