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VGMUL.VV

RISC-V VGMUL.VV Instruction Details

Instruction ManualR-type

Vector GHASH multiply: multiply 128-bit element groups in vd by hash subkey groups in vs2.

Instruction Syntax

vgmul.vv vd, vs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvkgVector CryptoGCM/GHASH
Related Search Terms
vgmul.vv instructionRISC-V vgmul.vvvgmul.vv syntaxvgmul.vv encodingZvkgvector GHASH field multiply

Instruction Behavior

vgmul.vv performs a GHASH field multiply over 128-bit element groups with SEW=32. It reads one operand from vd and the other from vs2, then writes the product back to vd.

Quick Understanding & Search Notes

VGMUL.VV is a Zvkg vector instruction for vector GHASH field multiply. This page is checked against the official vector crypto extension and V-extension execution model.

Performs GHASH GF(2^128) field multiplication over 128-bit element groups with SEW=32.
This element-group crypto instruction has no vm mask operand and executes at element-group granularity.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must hold at least one element group.
RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0RISC-V Unprivileged ISA Manual: V standard vector extension

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vgmul.vv vd, vs2».

Vector Acceleration

Understand this scenario with real code like «vgmul.vv vd, vs2».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

No vm operand; this element-group crypto instruction is not maskable.
Requires SEW=32, EGW=128. Multiplication by GHASH subkey H.
SEW=32, EGW=128, EGS=4; vl and vstart must be multiples of 4, and LMUL*VLEN must be at least 128.

FAQ

Can VGMUL.VV always use a v0.t mask?

No. This element-group crypto instruction has no vm operand; ordinary RVV mask syntax should not be added to examples.

What determines the element width for VGMUL.VV?

This instruction fixes SEW=32 and executes on 128-bit element groups; other SEW values are reserved/illegal cases.