VDIV.VX

RISC-V VDIV.VX Instruction Details

Q: Does VDIV.VX trap on divide by zero?

No. The official V extension defines the divide-by-zero result: the quotient is an all-ones bit pattern, and the instruction itself does not raise a divide-by-zero trap.

Q: How is VDIV.VX related to VREM?

VDIV.VX writes the quotient; the paired VREM form writes the remainder for the same divide relation. Both use the same divide-by-zero and signed-overflow special-case rules.

Q: How does VDIV.VX round the quotient?

The quotient rounds toward zero. At SEW=32, -21/4 produces -5, rather than -6. Ordinary masked forms compute only active elements.

Instruction ManualV-type

Vector-scalar signed integer division; writes each quotient to vd, and divide by zero does not trap.

Instruction Syntax

vdiv.vx vd, vs2, rs1[, v0.t]

Operand Breakdown

vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.

rs1 selects an integer register: use low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW (including unsigned division), and read zero from x0.

The quotient rounds toward zero; division by zero returns all ones without a divide-by-zero trap. Signed minimum/-1 returns the dividend; unsigned division cannot overflow.

Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.

VVector OperationsInteger Arithmetic

Related Search Terms

VDIV.VX instruction RISC-V VDIV.VX vdiv.vx syntax vdiv.vx encoding RVV signed quotient vdiv.vx divide zero vector-scalar quotient

Instruction Behavior

VDIV.VX divides each active signed SEW-bit vs2 element by the scalar formed from x[rs1] by the .vx rules, rounding the quotient toward zero into vd. A zero divisor returns all ones without a divide-by-zero trap; signed minimum/-1 returns the dividend.

VDIV.VX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VDIV computes each signed quotient and applies the official divide-by-zero and signed-overflow special cases.

Instruction input

vdiv.vx

vdUse v1-v31; v0 is the execution maskvs2Use v1-v31; v0 supplies the EEW=1 mask/carryrs1Use x0-x31 or ABI namevmexecution mask control

Execution Context

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 mask bitscontinuous 0/1 bit string

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvdiv.vx

funct6

100001

vs2

01000

rs1

01011

funct3

110

00100

opcode

1010111

lane

0x0064

0xffd6

0x8000

0x007f

0xffff

0x0001

0x0064

0xffd6

x11

0xffff

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vdiv.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed division, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VDIV.VX does not raise a divide-by-zero exception. For active elements within the current vl, it reads vs2 as the dividend and the x[rs1] scalar value as the divisor, writes the signed quotient, and with vm=0 only body elements whose v0.t bit is 1 execute.

VDIV.VX uses OP-V encoding; the .vx form is selected by funct3=110, and funct6=100001 selects VDIV.

vs2 is the dividend and the divisor comes from the x[rs1] scalar value; each lane is computed independently with no cross-lane combination.

Operands are interpreted as signed two's-complement SEW integers, and the result is the quotient.

The quotient rounds toward zero; integer divide does not use frm or vxrm and does not set floating-point exception flags.

When the divisor is zero, the quotient follows the official extreme-input rule: both unsigned and signed divide write an all-ones bit pattern.

For signed minimum divided by -1 overflow, VDIV writes the dividend and VREM writes zero.

With vm=0, v0.t is the execution mask; masked-off and tail elements follow the current vtype policies.

If XLEN>SEW, use the low SEW bits of x[rs1]; if XLEN<SEW, sign-extend to SEW, including for unsigned division.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, “V” Version 1.0

Vector Execution Context

vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.

rs1 selects an integer register: use low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW (including unsigned division), and read zero from x0.

The quotient rounds toward zero; division by zero returns all ones without a divide-by-zero trap. Signed minimum/-1 returns the dividend; unsigned division cannot overflow.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Vector Integer Scaling

Assume V/vector state enabled, vstart=0, supported e32,m1, VLMAX≥4, and a0=4. The example is unmasked, so all four body elements execute. v2=[20,21,22,23], a1=3 gives v1=[6,7,7,7]; quotients round toward zero. Tail elements follow ta without assumed zeroing.

Batch Quotients

Pre-Use Checklist

Syntax Check

vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
rs1 selects an integer register: use low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW (including unsigned division), and read zero from x0.

Semantic Check

The quotient rounds toward zero; division by zero returns all ones without a divide-by-zero trap. Signed minimum/-1 returns the dividend; unsigned division cannot overflow.
Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.

Pitfalls / Common Confusions

A zero divisor does not trap; software that needs an error path must test divisors explicitly.

The signed minimum divided by -1 case is architecturally defined: divide writes the dividend, and remainder writes zero.

The second source comes from x[rs1] and is formed as a SEW-width element by the .vx scalar rule; there is no scalar-divided-by-vector reverse form.

FAQ

Does VDIV.VX trap on divide by zero?