Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VREMU.VX
RISC-V VREMU.VX Instruction Details
Instruction ManualR-typevector-scalar unsigned integer remainder; writes each remainder to vd, and divide by zero does not trap.
Instruction Syntax
vremu.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerDivide/Remainder
Instruction Behavior
VREMU.VX is a RISC-V V extension vector-scalar unsigned integer remainder instruction. Each active element uses vs2 as the dividend and the x[rs1] scalar value as the divisor, computes the SEW-width remainder, and writes vd; zero divisors use the official specified result without a divide-by-zero trap.
VREMU.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VREMU computes each unsigned remainder and applies the official divide-by-zero and signed-overflow special cases.
Instruction input
vremu.vx
OP-V encodingvremu.vx
funct6
100010
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0064
0x002a
0x0007
0x00ff
0x0080
0x0001
0x0064
0x002a
%
%
%
%
%
%
%
%
x11
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vremu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned remainder, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VREMU.VX does not raise a divide-by-zero exception. For active elements within the current vl, it reads vs2 as the dividend and the x[rs1] scalar value as the divisor, writes the unsigned remainder, and with vm=0 only body elements whose v0.t bit is 1 execute.
VREMU.VX uses OP-V encoding; the .vx form is selected by funct3=110, and funct6=100010 selects VREMU.
vs2 is the dividend and the divisor comes from the x[rs1] scalar value; each lane is computed independently with no cross-lane combination.
Operands are interpreted as unsigned SEW integers, and the result is the remainder.
When the divisor is zero, the remainder result is the dividend SEW-bit pattern.
Unsigned forms have no signed minimum divided by -1 overflow special case.
With vm=0, v0.t is the execution mask; masked-off and tail elements follow the current vtype policies.
Vector Execution Context
When reading VREMU.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Modulo
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vremu.vx v8, v12, a1, v0.t».
Cyclic Indexing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vremu.vx v8, v12, a1, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
A zero divisor does not trap; software that needs an error path must test divisors explicitly.
Unsigned forms interpret both sources as SEW-width bit patterns and have no signed-overflow special case.
The second source comes from x[rs1] and is formed as a SEW-width element by the .vx scalar rule; there is no scalar-divided-by-vector reverse form.
FAQ
Does VREMU.VX trap on divide by zero?
No. The official V extension defines the divide-by-zero result: the remainder is the dividend, and the instruction itself does not raise a divide-by-zero trap.
How is VREMU.VX related to VDIVU?
VREMU.VX writes the remainder; the paired VDIVU form writes the quotient for the same divide relation. Both use the same unsigned divide-by-zero result rule.