Does VREMU.VV trap on divide by zero?
No. RVV integer divide/remainder uses the scalar extreme-input results; remainder instructions return the dividend when the divisor is zero.
VREMU.VV
RISC-V VREMU.VV Instruction Details
Instruction ManualR-typeElement-wise unsigned integer remainder.
Instruction Syntax
vremu.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerDivide/Remainder
Related Search Terms
Instruction Behavior
VREMU.VV computes unsigned remainders element-wise. A zero divisor does not trap; the remainder result is the dividend.
Quick Understanding & Search Notes
VREMU.VV is an RVV integer remainder instruction paired with the VDIV/VDIVU divide rules.
A zero divisor does not raise an exception; the remainder result is the dividend.
Operands are interpreted as unsigned integers.
vm=0 uses v0 as the execution mask; inactive and tail elements follow current policies.
Common Usage Scenarios
Modulo
Understand this scenario with real code like «vremu.vv v8, v12, v4, v0.t».
Cyclic Computation
Understand this scenario with real code like «vremu.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
A zero divisor returns the dividend as the remainder; the result is architecturally defined.
Operands are interpreted as unsigned integers.
There is no scalar-divided-by-vector remainder form.