Does VREMU.VV trap on divide by zero?
No. The official V extension defines the divide-by-zero result: the remainder is the dividend, and the instruction itself does not raise a divide-by-zero trap.
VREMU.VV
RISC-V VREMU.VV Instruction Details
Instruction ManualOPMVV (OP-V)vector-vector unsigned integer remainder; writes each remainder to vd, and divide by zero does not trap.
Instruction Syntax
vremu.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vremu.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=100010.
vs2[i] is the dividend; vs1[i] is the same-lane divisor. Compute unsigned SEW remainders. A zero divisor returns the dividend; unsigned division cannot overflow.
Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
Same-width sources/destination may overlap. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Steps are not processor cycles.
VVector IntegerDivide/Remainder
Instruction Behavior
VREMU.VV is a RISC-V V extension vector-vector unsigned integer remainder instruction. Each active element uses vs2 as the dividend and the same-lane vs1 element as the divisor, computes the SEW-width remainder, and writes vd; zero divisors use the official specified result without a divide-by-zero trap.
VREMU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows unsigned remainders and the zero-divisor result; unsigned division cannot overflow.
Instruction input
vremu.vv
Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. Fix VLEN=4096 and VLMAX=4096/16=256; equal-width sources/destination may overlap. Compute unsigned SEW remainders. A zero divisor returns the dividend. Masked vd cannot be v0; v0 cannot supply both mask and SEW data. Enter nonnegative element bit patterns. VL=0 leaves vd unchanged. Only body is shown; no definite inactive/tail values. Teaching stages are not processor cycles.
Execution Context
OP-V encodingvremu.vv
funct6
100010
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0064
0x002a
0x0007
0x00ff
0x0080
0x0001
0x0064
0x002a
%
%
%
%
%
%
%
%
v12
0x0009
0x0000
0x0004
0x0010
0x0003
0x0001
0x0009
0x0000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vremu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V field decode, active-element reads, unsigned remainder, mask control, and vd writeback. These are teaching stages; they do not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VREMU.VV does not raise a divide-by-zero exception. For active elements within the current vl, it reads vs2 as the dividend and the same-lane vs1 element as the divisor, writes the unsigned remainder, and with vm=0 only body elements whose v0.t bit is 1 execute.
32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=100010.
vs2 is the dividend and the divisor comes from the same-lane vs1 element; each lane is computed independently with no cross-lane combination.
Operands are interpreted as unsigned SEW integers, and the result is the remainder.
When the divisor is zero, the remainder result is the dividend SEW-bit pattern.
Unsigned forms have no signed minimum divided by -1 overflow special case.
With vm=0, v0.t is the execution mask; masked-off and tail elements follow the current vtype policies.
Require enabled vector state and valid supported vtype/SEW; vl=0 leaves vd unchanged.
Vector Execution Context
Syntax: vremu.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=100010.
vs2[i] is the dividend; vs1[i] is the same-lane divisor. Compute unsigned SEW remainders. A zero divisor returns the dividend; unsigned division cannot overflow.
Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
Same-width sources/destination may overlap. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Steps are not processor cycles.
Common Usage Scenarios
Element-wise unsigned remainder
Assume enabled V/VS, valid m1, supported SEW, VLEN≥128 and XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v12=[255,7,128,5], v4=[3,0,255,2] → v8=[0,7,128,1]. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
Masked vector remainder
Assume enabled V/VS, valid m1, supported SEW, VLEN≥128 and XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v12=[255,7,128,5], v4=[3,0,255,2] → v8=[0,7,128,1]. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vremu.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=100010.
- vs2[i] is the dividend; vs1[i] is the same-lane divisor. Compute unsigned SEW remainders. A zero divisor returns the dividend; unsigned division cannot overflow.
Semantic Check
- Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
- Same-width sources/destination may overlap. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Steps are not processor cycles.
Pitfalls / Common Confusions
A zero divisor does not trap; software that needs an error path must test divisors explicitly.
Unsigned forms interpret both sources as SEW-width bit patterns and have no signed-overflow special case.
The second source is the same-lane element of vs1; there is no scalar-divided-by-vector reverse form.
FAQ
How is VREMU.VV related to VDIVU?
VREMU writes the remainder; VDIVU writes the quotient. With a zero divisor, VREMU returns the dividend and VDIVU returns all ones. Unsigned division cannot overflow.