Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VDIVU.VV
RISC-V VDIVU.VV Instruction Details
Instruction ManualR-typevector-vector unsigned integer division; writes each quotient to vd, and divide by zero does not trap.
Instruction Syntax
vdivu.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsInteger Arithmetic
Instruction Behavior
VDIVU.VV is a RISC-V V extension vector-vector unsigned integer divide instruction. Each active element uses vs2 as the dividend and the same-lane vs1 element as the divisor, computes the SEW-width quotient, and writes vd; zero divisors use the official specified result without a divide-by-zero trap.
VDIVU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VDIVU computes each unsigned quotient and applies the official divide-by-zero and signed-overflow special cases.
Instruction input
vdivu.vv
OP-V encodingvdivu.vv
funct6
100000
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0064
0x002a
0x0007
0x00ff
0x0080
0x0001
0x0064
0x002a
/
/
/
/
/
/
/
/
v12
0x0009
0x0000
0x0004
0x0010
0x0003
0x0001
0x0009
0x0000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vdivu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned division, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VDIVU.VV does not raise a divide-by-zero exception. For active elements within the current vl, it reads vs2 as the dividend and the same-lane vs1 element as the divisor, writes the unsigned quotient, and with vm=0 only body elements whose v0.t bit is 1 execute.
VDIVU.VV uses OP-V encoding; the .vv form is selected by funct3=010, and funct6=100000 selects VDIVU.
vs2 is the dividend and the divisor comes from the same-lane vs1 element; each lane is computed independently with no cross-lane combination.
Operands are interpreted as unsigned SEW integers, and the result is the quotient.
When the divisor is zero, the quotient follows the official extreme-input rule: both unsigned and signed divide write an all-ones bit pattern.
Unsigned forms have no signed minimum divided by -1 overflow special case.
With vm=0, v0.t is the execution mask; masked-off and tail elements follow the current vtype policies.
Vector Execution Context
When reading VDIVU.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Integer Scaling
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vdivu.vv v1, v2, v3, v0.t».
Batch Quotients
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vdivu.vv v1, v2, v3, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
A zero divisor does not trap; software that needs an error path must test divisors explicitly.
Unsigned forms interpret both sources as SEW-width bit patterns and have no signed-overflow special case.
The second source is the same-lane element of vs1; there is no scalar-divided-by-vector reverse form.
FAQ
Does VDIVU.VV trap on divide by zero?
No. The official V extension defines the divide-by-zero result: the quotient is an all-ones bit pattern, and the instruction itself does not raise a divide-by-zero trap.
How is VDIVU.VV related to VREMU?
VDIVU.VV writes the quotient; the paired VREMU form writes the remainder for the same divide relation. Both use the same unsigned divide-by-zero result rule.