Does VDIVU.VV trap on divide by zero?
No. The official V extension defines the divide-by-zero result: the quotient is an all-ones bit pattern, and the instruction itself does not raise a divide-by-zero trap.
VDIVU.VV
RISC-V VDIVU.VV Instruction Details
Instruction ManualV-typeVector-vector unsigned integer division; writes each quotient to vd, and divide by zero does not trap.
Instruction Syntax
vdivu.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
vs1 supplies the SEW-wide same-lane divisor, while vs2 is the dividend; there is no immediate or reverse scalar-divided-by-vector form.
The quotient rounds toward zero; division by zero returns all ones without a divide-by-zero trap. Signed minimum/-1 returns the dividend; unsigned division cannot overflow.
Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.
VVector OperationsInteger Arithmetic
Instruction Behavior
VDIVU.VV divides each active unsigned SEW-bit vs2 element by its same-lane vs1 element, rounding the quotient toward zero into vd. A zero divisor returns all ones without a divide-by-zero trap; unsigned division cannot overflow.
VDIVU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VDIVU computes each unsigned quotient and its divide-by-zero result; unsigned division cannot overflow.
Instruction input
vdivu.vv
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvdivu.vv
funct6
100000
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0064
0x002a
0x0007
0x00ff
0x0080
0x0001
0x0064
0x002a
/
/
/
/
/
/
/
/
v12
0x0009
0x0000
0x0004
0x0010
0x0003
0x0001
0x0009
0x0000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vdivu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned division, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VDIVU.VV does not raise a divide-by-zero exception. For active elements within the current vl, it reads vs2 as the dividend and the same-lane vs1 element as the divisor, writes the unsigned quotient, and with vm=0 only body elements whose v0.t bit is 1 execute.
VDIVU.VV uses OP-V encoding; the .vv form is selected by funct3=010, and funct6=100000 selects VDIVU.
vs2 is the dividend and the divisor comes from the same-lane vs1 element; each lane is computed independently with no cross-lane combination.
Operands are interpreted as unsigned SEW integers, and the result is the quotient.
The quotient rounds toward zero; integer divide does not use frm or vxrm and does not set floating-point exception flags.
When the divisor is zero, the quotient follows the official extreme-input rule: both unsigned and signed divide write an all-ones bit pattern.
Unsigned forms have no signed minimum divided by -1 overflow special case.
With vm=0, v0.t is the execution mask; masked-off and tail elements follow the current vtype policies.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
vs1 supplies the SEW-wide same-lane divisor, while vs2 is the dividend; there is no immediate or reverse scalar-divided-by-vector form.
The quotient rounds toward zero; division by zero returns all ones without a divide-by-zero trap. Signed minimum/-1 returns the dividend; unsigned division cannot overflow.
Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.
Common Usage Scenarios
Vector Integer Scaling
Assume V/vector state enabled, vstart=0, supported e32,m1, VLMAX≥4, and a0=4. The example is unmasked, so all four body elements execute. v2=[20,21,22,23], v3=[3,4,5,6] gives v1=[6,5,4,3]; quotients round toward zero. Tail elements follow ta without assumed zeroing.
Batch Quotients
Assume V/vector state enabled, vstart=0, supported e32,m1, VLMAX≥4, and a0=4. The example is unmasked, so all four body elements execute. v2=[20,21,22,23], v3=[3,4,5,6] gives v1=[6,5,4,3]; quotients round toward zero. Tail elements follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
- vs1 supplies the SEW-wide same-lane divisor, while vs2 is the dividend; there is no immediate or reverse scalar-divided-by-vector form.
Semantic Check
- The quotient rounds toward zero; division by zero returns all ones without a divide-by-zero trap. Signed minimum/-1 returns the dividend; unsigned division cannot overflow.
- Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.
Pitfalls / Common Confusions
A zero divisor does not trap; software that needs an error path must test divisors explicitly.
Unsigned forms interpret both sources as SEW-width bit patterns and have no signed-overflow special case.
The second source is the same-lane element of vs1; there is no scalar-divided-by-vector reverse form.
FAQ
How is VDIVU.VV related to VREMU?
VDIVU.VV writes the quotient; the paired VREMU form writes the remainder. For a zero divisor, the quotient is all ones and the remainder equals the dividend.
How does VDIVU.VV round the quotient?
The quotient rounds toward zero. At SEW=32, 21/4 produces 5. Ordinary masked forms compute only active elements.