Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VREM.VV
RISC-V VREM.VV Instruction Details
Instruction ManualR-typevector-vector signed integer remainder; writes each remainder to vd, and divide by zero does not trap.
Instruction Syntax
vrem.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerDivide/Remainder
Instruction Behavior
VREM.VV is a RISC-V V extension vector-vector signed integer remainder instruction. Each active element uses vs2 as the dividend and the same-lane vs1 element as the divisor, computes the SEW-width remainder, and writes vd; zero divisors and signed overflow cases use the official specified results without a divide-by-zero trap.
VREM.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VREM computes each signed remainder and applies the official divide-by-zero and signed-overflow special cases.
Instruction input
vrem.vv
OP-V encodingvrem.vv
funct6
100011
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0064
0xffd6
0x8000
0x007f
0xffff
0x0001
0x0064
0xffd6
%
%
%
%
%
%
%
%
v12
0x0009
0x0000
0xffff
0xffff
0x0003
0x0001
0x0009
0x0000
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrem.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed remainder, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VREM.VV does not raise a divide-by-zero exception. For active elements within the current vl, it reads vs2 as the dividend and the same-lane vs1 element as the divisor, writes the signed remainder, and with vm=0 only body elements whose v0.t bit is 1 execute.
VREM.VV uses OP-V encoding; the .vv form is selected by funct3=010, and funct6=100011 selects VREM.
vs2 is the dividend and the divisor comes from the same-lane vs1 element; each lane is computed independently with no cross-lane combination.
Operands are interpreted as signed two's-complement SEW integers, and the result is the remainder.
When the divisor is zero, the remainder result is the dividend SEW-bit pattern.
For signed minimum divided by -1 overflow, VDIV writes the dividend and VREM writes zero.
With vm=0, v0.t is the execution mask; masked-off and tail elements follow the current vtype policies.
Vector Execution Context
When reading VREM.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Modulo
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vrem.vv v8, v12, v4, v0.t».
Cyclic Indexing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vrem.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
A zero divisor does not trap; software that needs an error path must test divisors explicitly.
The signed minimum divided by -1 case is architecturally defined: divide writes the dividend, and remainder writes zero.
The second source is the same-lane element of vs1; there is no scalar-divided-by-vector reverse form.
FAQ
Does VREM.VV trap on divide by zero?
No. The official V extension defines the divide-by-zero result: the remainder is the dividend, and the instruction itself does not raise a divide-by-zero trap.
How is VREM.VV related to VDIV?
VREM.VV writes the remainder; the paired VDIV form writes the quotient for the same divide relation. Both use the same divide-by-zero and signed-overflow special-case rules.