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VFMAX.VV

RISC-V VFMAX.VV Instruction Details

Instruction ManualR-type

VFMAX.VV is an RVV single-width floating-point maximum selection instruction with syntax vfmax.vv vd, vs2, vs1, vm; each active element compares vs2[i] with vs1[i] and writes the maximum to vd[i].

Instruction Syntax

vfmax.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Related Search Terms
VFMAX.VV instructionRISC-V VFMAX.VVvfmax.vv syntaxvfmax.vv encodingRVV FP maximumvfmax.vv mask executionFMIN FMAX NaN rules

Instruction Behavior

VFMAX.VV performs lane-wise floating-point maximum selection on active elements within vl. The second source is same-lane vs1[i]; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. NaN handling, signaling-NaN invalid flag, signed zero, and result selection follow the official RISC-V FMIN/FMAX rules; this is not integer min/max, saturation, or fused multiply-add.

VFMAX.VV Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise FP maximum selection with the second source from same-lane vs1.

Step 1 / 15
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input
vfmax.vv
Execution context
frm
RNE
demo dynamic rounding mode
vta/vma
ta, ma
tail/inactive policy
opcode
1010111
OP-V major opcode
Encoding fields
0x18861257
31..26
25
24..20
19..15
14..12
11..7
6..0
000110
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
max(1, 0.5)
1
i=1active
max(1.5, 1)
1.5
i=2skip
v0.t=0, not executed
--
i=3active
max(2.5, 2)
2.5
i=4active
max(-3, 2.5)
2.5
i=5active
max(3.5, 3)
3.5
i=6skip
v0.t=0, not executed
--
i=7active
max(4.5, 4)
4.5
This animation first represents demo input values as SEW=32 / binary32; min/max itself follows FMIN/FMAX selection semantics and is not selected by frm rounding mode. NaNs, infinities, signed zero, and exception flags still follow the official RVV/F FP rules and are not expanded here as a full FP exception simulator.

Quick Understanding & Search Notes

VFMAX.VV is best understood through OP-V encoding, same-lane vs1[i], v0.t masking, and per-active-element vd[i] = max(vs2[i], vs1[i]).

In the OP-V encoding, funct6=000110 and funct3=001 select the vector-vector FP maximum form for vfmax.vv.
The semantic operation is vd[i] = max(vs2[i], vs1[i]) for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
NaN handling, signaling-NaN invalid flag, signed zero, and value selection follow the official FMIN/FMAX rules.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
RISC-V Unprivileged ISA Manual: V extension vector floating-point instructionsRISC-V Unprivileged ISA Manual: F extension FMIN/FMAX semantics

Vector Execution Context

When reading VFMAX.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Lane-wise FP maximum

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmax.vv v1, v2, v3 # v1[i] = max(v2[i], v3[i])».

Upper-threshold selection

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmax.vv v1, v2, v3 # v1[i] = max(v2[i], v3[i])».

Vector numeric comparison

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmax.vv v1, v2, v3 # v1[i] = max(v2[i], v3[i])».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Operand order is vs2[i] and vs1[i] for maximum selection; do not treat it as a cross-lane reduction.
NaNs and signed zeros are not just ordinary numeric comparison; follow the official FMIN/FMAX rules.
This is not integer min/max, saturating clipping, or FMA; the result is a floating-point value selection.
Only active elements selected by v0.t execute; masked-off elements do not produce the min/max result shown on this page.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.

FAQ

What does the vm operand control for VFMAX.VV?

With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = max(vs2[i], vs1[i]).

Is VFMAX.VV a reduction min/max instruction?

No. It produces one destination vector element per lane; cross-element min/max reductions use the corresponding vector reduction instructions.

How does VFMAX.VV handle NaNs and signed zero?

These cases follow the official RISC-V FMIN/FMAX rules, including the invalid-flag rule for signaling NaNs; this page does not simplify them into integer-style comparison.