Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFMAX.VV
RISC-V VFMAX.VV Instruction Details
Instruction ManualR-typeCompare corresponding elements of vs2 and vs1, write the larger to vd.
Instruction Syntax
vfmax.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFMAX.VV compares floating-point operands element-wise and selects the maximum according to the RISC-V floating-point min/max rules. It is not an FMA instruction; NaN, signaling-NaN invalid-flag, and signed-zero behavior follow scalar FMIN/FMAX rules. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Quick Understanding & Search Notes
VFMAX.VV is vector FP maximum selection; interpret NaN and signed-zero behavior through FMIN/FMAX semantics.
A NaN paired with a numeric operand is not the same as ordinary NaN propagation; sNaN still sets invalid flag according to the rules.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Common Usage Scenarios
Element-wise Compare
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmax.vv v1, v2, v3 # v1[i] = max(v2[i], v3[i])».
Signal Processing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmax.vv v1, v2, v3 # v1[i] = max(v2[i], v3[i])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Do not model NaN handling as simple propagation whenever either operand is NaN; follow the RISC-V FMIN/FMAX rules.
This selects a min/max value; it is not saturation and not FMA.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.