Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFSGNJ.VV
RISC-V VFSGNJ.VV Instruction Details
Instruction ManualR-typeVFSGNJ.VV is an RVV single-width vector floating-point sign copy instruction with syntax vfsgnj.vv vd, vs2, vs1, vm; each active element keeps the non-sign bits of vs2[i] and forms vd[i] from the second-source sign bit.
Instruction Syntax
vfsgnj.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFSGNJ.VV performs lane-wise floating-point sign-bit composition on active elements within vl. The second source is same-lane vs1[i]; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. The official FSGNJ-class semantics are bit-pattern operations: non-sign bits come from vs2, the result sign is determined by the second-source sign bit, and no floating-point exception flags are set; this is not FP arithmetic, comparison, or cross-lane reduction.
VFSGNJ.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP sign injection: keep the non-sign bits of vs2 and take the sign from same-lane vs1.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfsgnj.vv
Execution context
frm
RNE
demo dynamic rounding modevta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodeEncoding fields
0x20861257
31..26
25
24..20
19..15
14..12
11..7
6..0
001000
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
bits 0x3fa00000 non-sign + sign(0x3f000000)
0x3fa00000 (1.25)
i=1active
bits 0xbfe00000 non-sign + sign(0x3f800000)
0x3fe00000 (1.75)
i=2skip
v0.t=0, not executed
--
i=3active
bits 0x40300000 non-sign + sign(0x40000000)
0x40300000 (2.75)
i=4active
bits 0xc0500000 non-sign + sign(0x40200000)
0x40500000 (3.25)
i=5active
bits 0x40700000 non-sign + sign(0x40400000)
0x40700000 (3.75)
i=6skip
v0.t=0, not executed
--
i=7active
bits 0xc0980000 non-sign + sign(0x40800000)
0x40980000 (4.75)
This animation composes SEW=32 / binary32 raw bit patterns: non-sign bits come from vs2, and the result sign is selected by the second-source sign. Inputs may be decimal demo values or 8-hex-digit bit patterns; FSGNJ-class instructions do not set FP exception flags.
Quick Understanding & Search Notes
VFSGNJ.VV is best understood through OP-V encoding, same-lane vs1[i], v0.t masking, and per-active-element vd[i] = {non-sign bits of vs2[i], sign(vs1[i])}.
In the OP-V encoding, funct6=001000 and funct3=001 select the vector-vector FP sign-injection form for VFSGNJ.VV.
The semantic operation is vd[i] = {non-sign bits of vs2[i], sign(vs1[i])} for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
FSGNJ-class instructions operate on the floating-point representation bit pattern and do not set floating-point exception flags.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
When reading VFSGNJ.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Lane-wise sign-bit copy
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnj.vv v1, v2, v3 # v1[i] takes non-sign bits from v2[i] and sign from v3[i]».
Vector copysign construction
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnj.vv v1, v2, v3 # v1[i] takes non-sign bits from v2[i] and sign from v3[i]».
Sign-bit teaching examples
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnj.vv v1, v2, v3 # v1[i] takes non-sign bits from v2[i] and sign from v3[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result is not numeric multiplication or ordinary arithmetic negation; it preserves the non-sign bits of vs2 and only replaces the sign bit.
VFSGNJ.VV's second source only supplies sign-selection information; it does not use the numeric magnitude of vs1[i].
FSGNJ-class instructions do not set floating-point exception flags; do not interpret NaN payload or exception behavior as arithmetic.
Only active elements selected by v0.t execute; masked-off elements do not produce the sign-injection result shown on this page.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
What does the vm operand control for VFSGNJ.VV?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = {non-sign bits of vs2[i], sign(vs1[i])}.
Is VFSGNJ.VV a floating-point arithmetic operation?
No. It is an FSGNJ-class bit-pattern operation that preserves the non-sign bits of vs2, combines a new sign bit, and does not set FP exception flags.
Does the numeric magnitude of the second source affect VFSGNJ.VV?
No. This instruction only uses sign-bit information from the second source; the non-sign bits of vs1[i] do not determine the result magnitude.