What does the vm operand control for VFSGNJ.VV?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = {non-sign bits of vs2[i], sign(vs1[i])}.
VFSGNJ.VV
RISC-V VFSGNJ.VV Instruction Details
Instruction ManualOP-VVFSGNJ.VV is an RVV single-width vector floating-point sign copy instruction with syntax vfsgnj.vv vd, vs2, vs1, vm; each active element keeps the non-sign bits of vs2[i] and forms vd[i] from the second-source sign bit.
Instruction Syntax
vfsgnj.vv vd, vs2, vs1, vm
Operand Breakdown
32-bit OP-V encoding: funct6=001000, funct3=001, opcode=1010111. vs1 selects a vector register; .vs reduction reads only element 0, while .vv reads per element.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
Non-sign bits come from vs2[i] and the sign comes from the second source. NaNs are not canonicalized, FP exceptions are not raised, and the result is not rounded by frm.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
VVector OperationsFloating-Point
Instruction Behavior
Active elements retain the non-sign bits of vs2[i] and take the sign of same-element vs1[i]. NaNs are not canonicalized and FP flags are not raised. vm=0 uses v0.t; vm=1 is unmasked.
VFSGNJ.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP sign injection: keep the non-sign bits of vs2 and take the sign from same-lane vs1.
Instruction input
vfsgnj.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm; the architectural instruction still requires valid frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x20861257
31..26
25
24..20
19..15
14..12
11..7
6..0
001000
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: bits 0x3fa00000 non-sign + sign(0x3f000000) -> 0x3fa00000 (1.25)
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
bits 0x3fa00000 non-sign + sign(0x3f000000)
0x3fa00000 (1.25)
i=1active
bits 0xbfe00000 non-sign + sign(0x3f800000)
0x3fe00000 (1.75)
i=2skip
v0.t=0, not executed
--
i=3active
bits 0x40300000 non-sign + sign(0x40000000)
0x40300000 (2.75)
i=4active
bits 0xc0500000 non-sign + sign(0x40200000)
0x40500000 (3.25)
i=5active
bits 0x40700000 non-sign + sign(0x40400000)
0x40700000 (3.75)
i=6skip
v0.t=0, not executed
--
i=7active
bits 0xc0980000 non-sign + sign(0x40800000)
0x40980000 (4.75)
This animation composes SEW=32 / binary32 raw bit patterns: non-sign bits come from vs2, and the result sign is selected by the second-source sign. Inputs may be decimal demo values or 8-hex-digit bit patterns; FSGNJ-class instructions do not set FP exception flags.
Quick Understanding & Search Notes
VFSGNJ.VV is best understood through OP-V encoding, same-lane vs1[i], v0.t masking, and per-active-element vd[i] = {non-sign bits of vs2[i], sign(vs1[i])}.
In the OP-V encoding, funct6=001000 and funct3=001 select the vector-vector FP sign-injection form for VFSGNJ.VV.
The semantic operation is vd[i] = {non-sign bits of vs2[i], sign(vs1[i])} for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
FSGNJ-class instructions operate on the floating-point representation bit pattern and do not set floating-point exception flags.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
32-bit OP-V encoding: funct6=001000, funct3=001, opcode=1010111. vs1 selects a vector register; .vs reduction reads only element 0, while .vv reads per element.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
Non-sign bits come from vs2[i] and the sign comes from the second source. NaNs are not canonicalized, FP exceptions are not raised, and the result is not rounded by frm.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Common Usage Scenarios
Lane-wise sign-bit copy
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3=[-1,1,-1,-1], v2=[1,-2,3,+0] → v1=[-1,2,-3,-0]. Tails follow ta without assumed zeroing.
Vector copysign construction
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3=[-1,1,-1,-1], v2=[1,-2,3,+0] → v1=[-1,2,-3,-0]. Tails follow ta without assumed zeroing.
Sign-bit teaching examples
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3=[-1,1,-1,-1], v2=[1,-2,3,+0] → v1=[-1,2,-3,-0]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V encoding: funct6=001000, funct3=001, opcode=1010111. vs1 selects a vector register; .vs reduction reads only element 0, while .vv reads per element.
- Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Semantic Check
- Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
- Non-sign bits come from vs2[i] and the sign comes from the second source. NaNs are not canonicalized, FP exceptions are not raised, and the result is not rounded by frm.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
- Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Pitfalls / Common Confusions
The result is not numeric multiplication or ordinary arithmetic negation; it preserves the non-sign bits of vs2 and only replaces the sign bit.
VFSGNJ.VV's second source only supplies sign-selection information; it does not use the numeric magnitude of vs1[i].
FSGNJ-class instructions do not set floating-point exception flags; do not interpret NaN payload or exception behavior as arithmetic.
With vm=0 only active elements selected by v0.t execute; vm=1 is unmasked.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
Is VFSGNJ.VV a floating-point arithmetic operation?
No. It is an FSGNJ-class bit-pattern operation that preserves the non-sign bits of vs2, combines a new sign bit, and does not set FP exception flags.
Does the numeric magnitude of the second source affect VFSGNJ.VV?
No. This instruction only uses sign-bit information from the second source; the non-sign bits of vs1[i] do not determine the result magnitude.