What does the vm operand control for VFSGNJX.VV?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = {non-sign bits of vs2[i], sign(vs2[i]) XOR sign(vs1[i])}.
VFSGNJX.VV
RISC-V VFSGNJX.VV Instruction Details
Instruction ManualOP-V / OPFVVVFSGNJX.VV is an RVV single-width vector floating-point XOR sign injection instruction with syntax vfsgnjx.vv vd, vs2, vs1[, v0.t]; each active element keeps the non-sign bits of vs2[i] and forms vd[i] from the XOR of the vs2[i] and second-source sign bits.
Instruction Syntax
vfsgnjx.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
32-bit OP-V encoding: funct6=001010, funct3=001, opcode=1010111. vs2 and vs1 supply the two same-lane vector sources.
The non-sign bits of vd[i] come from vs2[i]; its sign is the XOR of the vs2 and second-source signs. NaNs are not canonicalized, FP exceptions are not raised, and the result is not rounded by frm.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width destination/source overlap is legal; equal sources require equal initial bits. An ordinary masked destination cannot overlap v0; one source register cannot be read as both an EEW=1 mask and SEW-wide data.
Optional assembly v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Prestart elements do not update or raise exceptions. At vstart≥vl or vl=0 all destination elements, including tails, remain unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
V supplies FP32/FP64 and depends on F/D; these operations at SEW=16 require Zvfh. Require the extensions, supported widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without rounding or at vl=0; use of invalid frm is reserved.
The animation fixes VLEN=4096, LMUL=m1, vstart=0, valid frm=RNE, valid vtype, and enabled VS/FS. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32. Steps are educational, not processor cycles; input and exception limits are stated in the animation.
VVector OperationsFloating-Point
Instruction Behavior
VFSGNJX.VV performs lane-wise floating-point sign-bit composition on active elements within vl. The second source is same-lane vs1[i]; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. The official FSGNJ-class semantics are bit-pattern operations: non-sign bits come from vs2, the result sign is determined by the XOR of the vs2[i] and second-source sign bits, and no floating-point exception flags are set; this is not FP arithmetic, comparison, or cross-lane reduction. V defines SEW=32 and SEW=64; Zvfh is required only for SEW=16.
VFSGNJX.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP sign injection: keep the non-sign bits of vs2 and take the sign from the XOR of vs2 and same-lane vs1 signs.
Instruction input
vfsgnjx.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm; the architectural instruction still requires valid frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x28861257
31..26
25
24..20
19..15
14..12
11..7
6..0
001010
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: bits 0x3fa00000 non-sign + sign XOR(0x3fa00000, 0x3f000000) -> 0x3fa00000 (1.25)
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
bits 0x3fa00000 non-sign + sign XOR(0x3fa00000, 0x3f000000)
0x3fa00000 (1.25)
i=1active
bits 0xbfe00000 non-sign + sign XOR(0xbfe00000, 0x3f800000)
0xbfe00000 (-1.75)
i=2skip
v0.t=0, not executed
--
i=3active
bits 0x40300000 non-sign + sign XOR(0x40300000, 0x40000000)
0x40300000 (2.75)
i=4active
bits 0xc0500000 non-sign + sign XOR(0xc0500000, 0x40200000)
0xc0500000 (-3.25)
i=5active
bits 0x40700000 non-sign + sign XOR(0x40700000, 0x40400000)
0x40700000 (3.75)
i=6skip
v0.t=0, not executed
--
i=7active
bits 0xc0980000 non-sign + sign XOR(0xc0980000, 0x40800000)
0xc0980000 (-4.75)
This animation composes SEW=32 / binary32 raw bit patterns: non-sign bits come from vs2, and the result sign is selected by the XOR of the vs2 and second-source signs. Inputs may be decimal demo values or 8-hex-digit bit patterns; FSGNJ-class instructions do not set FP exception flags.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, and valid frm=RNE, with the selected binary32/64 supported. Equal source registers require equal initial bits; same-width destination/source overlap is legal.VL=0 updates no destination elements, including tails; inactive and tail values follow ma/ta without definite displayed values. Sign injection preserves the vs2 NaN payload and does not set fflags; it does not round by frm, but the architectural instruction still requires valid frm.
Quick Understanding & Search Notes
VFSGNJX.VV is best understood through OP-V encoding, same-lane vs1[i], v0.t masking, and per-active-element vd[i] = {non-sign bits of vs2[i], sign(vs2[i]) XOR sign(vs1[i])}.
In the OP-V encoding, funct6=001010 and funct3=001 select the vector-vector FP sign-injection form for VFSGNJX.VV.
The semantic operation is vd[i] = {non-sign bits of vs2[i], sign(vs2[i]) XOR sign(vs1[i])} for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
FSGNJ-class instructions operate on the floating-point representation bit pattern and do not set floating-point exception flags. NaNs are not canonicalized; the non-sign bits of vs2, including NaN payloads, are preserved.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
The optional assembly operand v0.t corresponds to vm=0; omitting it gives vm=1. Active elements satisfy vstart ≤ i < vl and the mask condition; VL=0 updates no destination elements, including tails.
Every vector FP instruction requires valid frm, including instructions that do not round and executions with VL=0; use of an invalid frm is reserved.
Vector Execution Context
32-bit OP-V encoding: funct6=001010, funct3=001, opcode=1010111. vs2 and vs1 supply the two same-lane vector sources.
The non-sign bits of vd[i] come from vs2[i]; its sign is the XOR of the vs2 and second-source signs. NaNs are not canonicalized, FP exceptions are not raised, and the result is not rounded by frm.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width destination/source overlap is legal; equal sources require equal initial bits. An ordinary masked destination cannot overlap v0; one source register cannot be read as both an EEW=1 mask and SEW-wide data.
Optional assembly v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Prestart elements do not update or raise exceptions. At vstart≥vl or vl=0 all destination elements, including tails, remain unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
V supplies FP32/FP64 and depends on F/D; these operations at SEW=16 require Zvfh. Require the extensions, supported widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without rounding or at vl=0; use of invalid frm is reserved.
The animation fixes VLEN=4096, LMUL=m1, vstart=0, valid frm=RNE, valid vtype, and enabled VS/FS. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32. Steps are educational, not processor cycles; input and exception limits are stated in the animation.
Common Usage Scenarios
Lane-wise conditional sign flip
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3=[-1,1,-1,-1], v2=[1,-2,3,+0] → v1=[-1,-2,-3,-0]. Tails follow ta without assumed zeroing.
Sign-bit XOR
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3=[-1,1,-1,-1], v2=[1,-2,3,+0] → v1=[-1,-2,-3,-0]. Tails follow ta without assumed zeroing.
Vector absolute-value / negation construction
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3=[-1,1,-1,-1], v2=[1,-2,3,+0] → v1=[-1,-2,-3,-0]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V encoding: funct6=001010, funct3=001, opcode=1010111. vs2 and vs1 supply the two same-lane vector sources.
- The non-sign bits of vd[i] come from vs2[i]; its sign is the XOR of the vs2 and second-source signs. NaNs are not canonicalized, FP exceptions are not raised, and the result is not rounded by frm.
Semantic Check
- Vector operands and results have SEW bits and EMUL=LMUL. Same-width destination/source overlap is legal; equal sources require equal initial bits. An ordinary masked destination cannot overlap v0; one source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Optional assembly v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Prestart elements do not update or raise exceptions. At vstart≥vl or vl=0 all destination elements, including tails, remain unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
- V supplies FP32/FP64 and depends on F/D; these operations at SEW=16 require Zvfh. Require the extensions, supported widths, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without rounding or at vl=0; use of invalid frm is reserved.
- The animation fixes VLEN=4096, LMUL=m1, vstart=0, valid frm=RNE, valid vtype, and enabled VS/FS. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32. Steps are educational, not processor cycles; input and exception limits are stated in the animation.
Pitfalls / Common Confusions
The result is not numeric multiplication or ordinary arithmetic negation; it preserves the non-sign bits of vs2 and only replaces the sign bit.
VFSGNJX.VV's second source only supplies sign-selection information; it does not use the numeric magnitude of vs1[i].
FSGNJ-class instructions do not set floating-point exception flags; do not interpret NaN payload or exception behavior as arithmetic.
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. Masked-off elements do not produce a sign-injection result.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
Is VFSGNJX.VV a floating-point arithmetic operation?
No. It is an FSGNJ-class bit-pattern operation that preserves the non-sign bits of vs2, combines a new sign bit, and does not set FP exception flags.
Does the numeric magnitude of the second source affect VFSGNJX.VV?
No. This instruction only uses sign-bit information from the second source; the non-sign bits of vs1[i] do not determine the result magnitude.