Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFSGNJX.VF
RISC-V VFSGNJX.VF Instruction Details
Instruction ManualR-typeVFSGNJX.VF is an RVV single-width vector floating-point scalar XOR sign injection instruction with syntax vfsgnjx.vf vd, vs2, rs1, vm; each active element keeps the non-sign bits of vs2[i] and forms vd[i] from the XOR of the vs2[i] and scalar f[rs1] sign bits.
Instruction Syntax
vfsgnjx.vf vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFSGNJX.VF performs lane-wise floating-point sign-bit composition on active elements within vl. The second source is scalar FP register f[rs1]; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. The official FSGNJ-class semantics are bit-pattern operations: non-sign bits come from vs2, the result sign is determined by the XOR of the vs2[i] and scalar f[rs1] sign bits, and no floating-point exception flags are set; this is not FP arithmetic, comparison, or cross-lane reduction.
VFSGNJX.VF Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP sign injection: keep the non-sign bits of vs2 and take the sign from the XOR of vs2 and scalar f[rs1] signs.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Instruction input
vfsgnjx.vf
Execution context
frm
RNE
demo dynamic rounding modevta/vma
ta, ma
tail/inactive policyopcode
1010111
OP-V major opcodeEncoding fields
0x28855257
31..26
25
24..20
19..15
14..12
11..7
6..0
001010
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
bits 0x3fa00000 non-sign + sign XOR(0x3fa00000, 0x3fc00000)
0x3fa00000 (1.25)
i=1active
bits 0xbfe00000 non-sign + sign XOR(0xbfe00000, 0x3fc00000)
0xbfe00000 (-1.75)
i=2skip
v0.t=0, not executed
--
i=3active
bits 0x40300000 non-sign + sign XOR(0x40300000, 0x3fc00000)
0x40300000 (2.75)
i=4active
bits 0xc0500000 non-sign + sign XOR(0xc0500000, 0x3fc00000)
0xc0500000 (-3.25)
i=5active
bits 0x40700000 non-sign + sign XOR(0x40700000, 0x3fc00000)
0x40700000 (3.75)
i=6skip
v0.t=0, not executed
--
i=7active
bits 0xc0980000 non-sign + sign XOR(0xc0980000, 0x3fc00000)
0xc0980000 (-4.75)
This animation composes SEW=32 / binary32 raw bit patterns: non-sign bits come from vs2, and the result sign is selected by the XOR of the vs2 and second-source signs. Inputs may be decimal demo values or 8-hex-digit bit patterns; FSGNJ-class instructions do not set FP exception flags.
Quick Understanding & Search Notes
VFSGNJX.VF is best understood through OP-V encoding, scalar FP register f[rs1], v0.t masking, and per-active-element vd[i] = {non-sign bits of vs2[i], sign(vs2[i]) XOR sign(f[rs1])}.
In the OP-V encoding, funct6=001010 and funct3=101 select the vector-scalar FP sign-injection form for VFSGNJX.VF.
The semantic operation is vd[i] = {non-sign bits of vs2[i], sign(vs2[i]) XOR sign(f[rs1])} for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
FSGNJ-class instructions operate on the floating-point representation bit pattern and do not set floating-point exception flags.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
Vector Execution Context
When reading VFSGNJX.VF, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vf: one vector source and one floating-point scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Conditionally flip vector signs from a scalar
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnjx.vf v1, v2, ft0 # v1[i] takes non-sign bits from v2[i] and sign(v2[i]) XOR sign(ft0)».
Sign-bit XOR
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnjx.vf v1, v2, ft0 # v1[i] takes non-sign bits from v2[i] and sign(v2[i]) XOR sign(ft0)».
Vector absolute-value / negation construction
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnjx.vf v1, v2, ft0 # v1[i] takes non-sign bits from v2[i] and sign(v2[i]) XOR sign(ft0)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The result is not numeric multiplication or ordinary arithmetic negation; it preserves the non-sign bits of vs2 and only replaces the sign bit.
VFSGNJX.VF's second source only supplies sign-selection information; it does not use f[rs1] as a scalar multiplier.
FSGNJ-class instructions do not set floating-point exception flags; do not interpret NaN payload or exception behavior as arithmetic.
Only active elements selected by v0.t execute; masked-off elements do not produce the sign-injection result shown on this page.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
What does the vm operand control for VFSGNJX.VF?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = {non-sign bits of vs2[i], sign(vs2[i]) XOR sign(f[rs1])}.
Is VFSGNJX.VF a floating-point arithmetic operation?
No. It is an FSGNJ-class bit-pattern operation that preserves the non-sign bits of vs2, combines a new sign bit, and does not set FP exception flags.
Does the numeric magnitude of the second source affect VFSGNJX.VF?
No. This instruction only uses sign-bit information from the second source; the non-sign bits of f[rs1] do not determine the result magnitude.