Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFSGNJ.VF
RISC-V VFSGNJ.VF Instruction Details
Instruction ManualR-typeCombine magnitude of vs2[i] with sign of f[rs1]: vd[i] = vs2[i] * sign(f[rs1]).
Instruction Syntax
vfsgnj.vf vd, vs2, rs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFSGNJ.VF performs floating-point sign injection: it combines sign bits without numerical arithmetic. The magnitude bits come from vs2, and the sign comes from f[rs1] copied directly. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
VFSGNJ.VF is a bit-level sign operation, commonly used for copy-sign, negate, or sign-XOR vector work.
Sign injection is not a numeric comparison and is not arithmetic multiplication by +1/-1.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Common Usage Scenarios
Sign Copy
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnj.vf v1, v2, ft0 # v1[i] = v2[i] with sign of ft0».
Absolute Value
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsgnj.vf v1, v2, ft0 # v1[i] = v2[i] with sign of ft0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Bitwise op, no FP exceptions. vfsgnj=direct sign (f[rs1] sign).
vfsgnjn=negated sign. vfsgnjx=XOR sign.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.