What does the vm operand control for VFMIN.VV?
With vm=0, only active elements selected by v0.t execute; vm=1 is unmasked. The page formula is vd[i] = min(vs2[i], vs1[i]).
VFMIN.VV
RISC-V VFMIN.VV Instruction Details
Instruction ManualV-typeVFMIN.VV is an RVV single-width floating-point minimum selection instruction with syntax vfmin.vv vd, vs2, vs1, vm; each active element compares vs2[i] with vs1[i] and writes the minimum to vd[i].
Instruction Syntax
vfmin.vv vd, vs2, vs1, vm
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is legal and equal sources read equal initial values. There is no immediate operand.
vs1 provides the second SEW-wide FP value in the same lane; this is not a cross-lane reduction.
Assembly vm is optional v0.t; omission means vm=1. Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) perform minimumNumber/maximumNumber.
Require V, supported vtype and FP widths, and enabled VS/FS; V supports FP32/FP64 and depends on F/D. With H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even if no rounding occurs or vl=0.
Prestart is unchanged; vl=0 or vstart≥vl leaves every destination element, including tails, unchanged. Otherwise inactive/tail elements follow vma/vta, with no guaranteed zeroing or preservation.
With vm=0, vd cannot overlap v0; v0 cannot supply both an EEW=1 selection/mask source and SEW data. Successful execution resets vstart to zero.
VVector OperationsFloating-Point
Instruction Behavior
VFMIN.VV performs lane-wise floating-point minimum selection on active elements within vl. The second source is same-lane vs1[i]; with vm=0, v0.t controls which elements execute, and vm=1 is unmasked. NaN handling, signaling-NaN invalid flag, signed zero, and result selection follow the official RISC-V FMIN/FMAX rules; this is not integer min/max, saturation, or fused multiply-add.
VFMIN.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP minimum selection with the second source from same-lane vs1.
Instruction input
vfmin.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm; the architectural instruction still requires valid frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x10861257
31..26
25
24..20
19..15
14..12
11..7
6..0
000100
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: min(1, 0.5) -> 0x3f000000 (0.5)
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
This execution does not raise NVLong vectors scroll inside this module without page overflow.
i=0active
min(1, 0.5)
0x3f000000 (0.5)
i=1active
min(1.5, 1)
0x3f800000 (1)
i=2skip
v0.t=0, not executed
--
i=3active
min(2.5, 2)
0x40000000 (2)
i=4active
min(-3, 2.5)
0xc0400000 (-3)
i=5active
min(3.5, 3)
0x40400000 (3)
i=6skip
v0.t=0, not executed
--
i=7active
min(4.5, 4)
0x40800000 (4)
Inputs are first represented as SEW=32 / binary32, then FMIN/FMAX selects: one NaN returns the other input, two NaNs return canonical NaN, and any active sNaN raises NV. -0 is less than +0; equal-sign zeros retain their sign. Selection does not round by frm, but the architectural instruction still requires valid frm. The NV indicator shows what this execution raises, not a clearing or full snapshot of existing fflags.
This teaching context fixes VS/FS enabled, valid vtype, frm=RNE, and FLEN=64; a SEW=32 scalar input represents the low 32 bits of a valid NaN box. Equal sources require equal bits. Same-width destination/source overlap is legal; ta/ma gives no definite inactive or tail value. At VL=0 no destination elements, including tails, are updated.
Quick Understanding & Search Notes
VFMIN.VV is best understood through OP-V encoding, same-lane vs1[i], v0.t masking, and per-active-element vd[i] = min(vs2[i], vs1[i]).
In the OP-V encoding, funct6=000100 and funct3=001 select the vector-vector FP minimum form for vfmin.vv.
The semantic operation is vd[i] = min(vs2[i], vs1[i]) for active elements within vl.
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
One NaN input returns the non-NaN input; two NaNs return canonical NaN. Any signaling NaN raises fflags.NV even when a number is returned; quiet NaN alone does not. For min/max, -0.0 is less than +0.0; equal-sign zeros retain their sign.
For ordinary masked vector instructions, the destination vector register group must not overlap the v0 mask source; the animation rejects vd=v0 when vm=0.
This page covers V 1.0: V depends on F/D and supports FP SEW=32/64; VS/FS must be enabled and vtype valid. An invalid frm is reserved even though this operation does not round by frm.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is legal and equal sources read equal initial values. There is no immediate operand.
vs1 provides the second SEW-wide FP value in the same lane; this is not a cross-lane reduction.
Assembly vm is optional v0.t; omission means vm=1. Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) perform minimumNumber/maximumNumber.
Require V, supported vtype and FP widths, and enabled VS/FS; V supports FP32/FP64 and depends on F/D. With H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even if no rounding occurs or vl=0.
Prestart is unchanged; vl=0 or vstart≥vl leaves every destination element, including tails, unchanged. Otherwise inactive/tail elements follow vma/vta, with no guaranteed zeroing or preservation.
With vm=0, vd cannot overlap v0; v0 cannot supply both an EEW=1 selection/mask source and SEW data. Successful execution resets vstart to zero.
Common Usage Scenarios
Lane-wise FP minimum
Assume V/VS/FS enabled, valid frm, supported e32,m1, VLMAX≥4, x10=4, vstart=0, and v2=[1,-2,3,+0]; scalars are validly NaN-boxed. v3=[2,-3,1,-0] → v1=[1,-3,1,-0]. Min/max examples omit v0.t, so all four body elements execute; merge uses v0 only for selection. Tails follow ta without assumed zeroing.
Upper-bound clipping
Assume V/VS/FS enabled, valid frm, supported e32,m1, VLMAX≥4, x10=4, vstart=0, and v2=[1,-2,3,+0]; scalars are validly NaN-boxed. v3=[2,-3,1,-0] → v1=[1,-3,1,-0]. Min/max examples omit v0.t, so all four body elements execute; merge uses v0 only for selection. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is legal and equal sources read equal initial values. There is no immediate operand.
- vs1 provides the second SEW-wide FP value in the same lane; this is not a cross-lane reduction.
Semantic Check
- Assembly vm is optional v0.t; omission means vm=1. Only active elements with vstart≤i<vl and (vm=1 or v0[i]=1) perform minimumNumber/maximumNumber.
- Require V, supported vtype and FP widths, and enabled VS/FS; V supports FP32/FP64 and depends on F/D. With H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even if no rounding occurs or vl=0.
- Prestart is unchanged; vl=0 or vstart≥vl leaves every destination element, including tails, unchanged. Otherwise inactive/tail elements follow vma/vta, with no guaranteed zeroing or preservation.
- With vm=0, vd cannot overlap v0; v0 cannot supply both an EEW=1 selection/mask source and SEW data. Successful execution resets vstart to zero.
Pitfalls / Common Confusions
Operand order is vs2[i] and vs1[i] for minimum selection; do not treat it as a cross-lane reduction.
NaNs and signed zeros are not just ordinary numeric comparison; follow the official FMIN/FMAX rules.
This is not integer min/max, saturating clipping, or FMA; the result is a floating-point value selection.
With vm=0, only v0.t=1 active elements execute; with vm=1, all body elements execute. Masked-off elements follow vma and are not guaranteed to be zero or preserved.
When vm=0 uses v0.t as the execution mask, the ordinary destination vector register group must not overlap the v0 mask register.
FAQ
Is VFMIN.VV a reduction min/max instruction?
No. It produces one destination vector element per lane; cross-element min/max reductions use the corresponding vector reduction instructions.
How does VFMIN.VV handle NaNs and signed zero?
One NaN input returns the non-NaN input; two NaNs return canonical NaN. Any signaling NaN raises fflags.NV even when a number is returned; quiet NaN alone does not. For min/max, -0.0 is less than +0.0; equal-sign zeros retain their sign.