How does VMIN.VV differ from the unsigned form?
VMIN.VV uses signed integer ordering; the corresponding U form uses unsigned integer ordering. Both write back the selected source element's SEW-bit pattern.
VMIN.VV
RISC-V VMIN.VV Instruction Details
Instruction ManualOP-V (OPIVV)Select the smaller value element by signed integer ordering and write the selected SEW-bit pattern to vd.
Instruction Syntax
vmin.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Compare vs2[i] with vs1[i] in SEW-wide two's-complement signed order and write the smaller source bit pattern to vd[i]; vxsat and fflags are not set.
32-bit OP-V: opcode=1010111, funct6=000101, funct3=000. [, v0.t] is optional: omitted means vm=1; included means vm=0.
Sources/destination have EEW=SEW and EMUL=LMUL; same-width overlap is legal and equal sources require equal initial values. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
VVector IntegerMin/Max
Instruction Behavior
VMIN.VV is the RISC-V V extension vector-vector signed minimum instruction. Each active body element reads vs2[i] and vs1[i], compares them by signed integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.
VMIN.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMIN compares active elements as signed integers and writes the smaller SEW-bit pattern to vd.
Instruction input
vmin.vv
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmin.vv
funct6
000101
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
min
min
min
min
min
min
min
min
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmin.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed minimum, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMIN.VV compares vs2 with vs1 lane by lane for active elements within the current vl and selects the smaller value by signed integer ordering. The result is the selected source element's SEW-bit pattern written to vd; it does not compute a difference or set vxsat or fflags.
VMIN uses OP-V vector-arithmetic encoding with funct6=000101; the .vv form is selected by funct3=000.
The core semantic relation compares vs2[i] with vs1[i] for active elements by signed integer ordering, then writes the smaller value's original SEW-bit pattern to vd[i].
VMIN/VMAX use signed integer ordering; the sign bit is interpreted at SEW width for comparison, but the selected source element pattern is written back unchanged.
Only body elements within the current vl are processed; vm=0 uses the v0 mask and vm=1 is unmasked, while mask-off and tail destination elements follow the current vtype policies.
Require valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged; vl=0 or vstart≥vl updates no destination elements, including tails.
Same-EEW sources/destination may overlap. A masked vd cannot include v0, and v0 cannot supply both EEW=1 mask and SEW data.
Vector Execution Context
Compare vs2[i] with vs1[i] in SEW-wide two's-complement signed order and write the smaller source bit pattern to vd[i]; vxsat and fflags are not set.
32-bit OP-V: opcode=1010111, funct6=000101, funct3=000. [, v0.t] is optional: omitted means vm=1; included means vm=0.
Sources/destination have EEW=SEW and EMUL=LMUL; same-width overlap is legal and equal sources require equal initial values. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Common Usage Scenarios
Data Clipping
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v0.t used; v8=[0xffffffff,2,0x80000000,7], v12=[3,3,3,3], v0.mask=[1,0,1,1] → v4=[0xffffffff,policy,0x80000000,3]. policy retains the old value or writes all ones; tails are not guaranteed zero.
Thresholding
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v0.t used; v8=[0xffffffff,2,0x80000000,7], v12=[3,3,3,3], v0.mask=[1,0,1,1] → v4=[0xffffffff,policy,0x80000000,3]. policy retains the old value or writes all ones; tails are not guaranteed zero.
Pre-Use Checklist
Syntax Check
- Compare vs2[i] with vs1[i] in SEW-wide two's-complement signed order and write the smaller source bit pattern to vd[i]; vxsat and fflags are not set.
- 32-bit OP-V: opcode=1010111, funct6=000101, funct3=000. [, v0.t] is optional: omitted means vm=1; included means vm=0.
Semantic Check
- Sources/destination have EEW=SEW and EMUL=LMUL; same-width overlap is legal and equal sources require equal initial values. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data.
- Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Pitfalls / Common Confusions
VMIN selects one source element pattern; it is not addition, subtraction, or a saturating operation.
Signed forms interpret each SEW-wide source element as a two's-complement signed integer, so a value with the top bit set can be smaller than one with the top bit clear.
The VV form takes its second source from vector register vs1 and does not read an integer scalar register.
With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.
FAQ
Does VMIN.VV set vxsat or fflags?
No. It compares by signed ordering and selects source bits; it is neither saturating nor floating-point arithmetic. Vector configuration and state requirements still apply.
How do vm and v0.t affect VMIN.VV?
With vm=0, only body elements whose v0.t bit is 1 execute the compare; with vm=1, body elements within the current vl are active. Masked-off and tail destination elements follow the current vtype policies.