Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMINU.VV
RISC-V VMINU.VV Instruction Details
Instruction ManualR-typeSelect the smaller value element by unsigned integer ordering and write the selected SEW-bit pattern to vd.
Instruction Syntax
vminu.vv vd, vs2, vs1, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerMin/Max
Instruction Behavior
VMINU.VV is the RISC-V V extension vector-vector unsigned minimum instruction. Each active body element reads vs2[i] and vs1[i], compares them by unsigned integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.
VMINU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMINU compares active elements as unsigned integers and writes the smaller SEW-bit pattern to vd.
Instruction input
vminu.vv
OP-V encodingvminu.vv
funct6
000100
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
min
min
min
min
min
min
min
min
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vminu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned minimum, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMINU.VV compares vs2 with vs1 lane by lane for active elements within the current vl and selects the smaller value by unsigned integer ordering. The result is the selected source element's SEW-bit pattern written to vd; it does not compute a difference or produce overflow or exception flags.
VMINU uses OP-V vector-arithmetic encoding with funct6=000100; the .vv form is selected by funct3=000.
The core semantic relation compares vs2[i] with vs1[i] for active elements by unsigned integer ordering, then writes the smaller value's original SEW-bit pattern to vd[i].
VMINU/VMAXU use unsigned integer ordering; comparison and selection use the SEW-width unsigned values.
Only body elements within the current vl are processed; vm=0 uses the v0 mask and vm=1 is unmasked, while mask-off and tail destination elements follow the current vtype policies.
Vector Execution Context
When reading VMINU.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Data Clipping
Understand this scenario with real code like «vminu.vv v4, v8, v12, v0.t».
Thresholding
Understand this scenario with real code like «vminu.vv v4, v8, v12, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VMINU selects one source element pattern; it is not addition, subtraction, or a saturating operation.
Unsigned forms compare the SEW bit patterns as unsigned integers, so a value with the top bit set is usually larger than one with the top bit clear.
The VV form takes its second source from vector register vs1 and does not read an integer scalar register.
With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.
FAQ
How does VMINU.VV differ from the signed form?
VMINU.VV uses unsigned integer ordering; the non-U form uses signed integer ordering. Both write back the selected source element's SEW-bit pattern.
Does VMINU.VV produce overflow or exception flags?
No. VMINU.VV compares and selects a source element pattern; it does not perform add/subtract overflow computation and does not set integer or floating-point exception flags.
How do vm and v0.t affect VMINU.VV?
With vm=0, only body elements whose v0.t bit is 1 execute the compare; with vm=1, body elements within the current vl are active. Masked-off and tail destination elements follow the current vtype policies.