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VMINU.VV

RISC-V VMINU.VV Instruction Details

Instruction ManualV-type

Select the smaller value element by unsigned integer ordering and write the selected SEW-bit pattern to vd.

Instruction Syntax

vminu.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Compare vs2[i] with vs1[i] in SEW-wide unsigned order; write the smaller source bits to vd[i]. This sets neither vxsat nor fflags.
32-bit OP-V: opcode=1010111, funct6=000100, funct3=000. [, v0.t] is optional: omitted means vm=1; included means vm=0.
Same-width source/destination overlap is legal; equal sources require equal initial values. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive elements follow vma; tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
VVector IntegerMin/Max
Related Search Terms
VMINU.VV instructionRISC-V VMINU.VVvminu.vv syntaxvminu.vv encodingRVV unsigned minimumvminu.vv maskunsigned vector compare

Instruction Behavior

VMINU.VV is the RISC-V V extension vector-vector unsigned minimum instruction. Each active body element reads vs2[i] and vs1[i], compares them by unsigned integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.

VMINU.VV Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMINU compares active elements as unsigned integers and writes the smaller SEW-bit pattern to vd.

Instruction input
vminu.vv

Require valid vtype, enabled VS, and supported SEW; VL=0 updates no destination, including tails. An ordinary masked vd cannot be v0; v0 cannot supply both mask and SEW data. Same-width source/destination overlap is legal.

Execution Context

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvminu.vv
funct6
000100
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
min
min
min
min
min
min
min
min
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step

Show OP-V 32-bit encoding fields

vminu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned minimum, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMINU.VV writes the smaller SEW-bit pattern from vs2[i] and vs1[i] to vd[i] for active body elements, using unsigned ordering.

32-bit OP-V: opcode=1010111, funct6=000100, funct3=000.
Select the smaller source bit pattern by SEW-wide unsigned integer order.
VV reads vs2[i] and vs1[i], not an integer scalar.
vm=0 uses v0.t; inactive elements follow vma and tails follow vta.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — V 1.0

Vector Execution Context

Compare vs2[i] with vs1[i] in SEW-wide unsigned order; write the smaller source bits to vd[i]. This sets neither vxsat nor fflags.

32-bit OP-V: opcode=1010111, funct6=000100, funct3=000. [, v0.t] is optional: omitted means vm=1; included means vm=0.

Same-width source/destination overlap is legal; equal sources require equal initial values. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data.

Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive elements follow vma; tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Data Clipping

Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v0.t used; v8=[0xffffffff,2,0x80000000,7], v12=[3,3,3,3], v0.mask=[1,0,1,1] → v4=[3,policy,3,3]. policy retains the old value or writes all ones; tails are not guaranteed zero.

Thresholding

Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v0.t used; v8=[0xffffffff,2,0x80000000,7], v12=[3,3,3,3], v0.mask=[1,0,1,1] → v4=[3,policy,3,3]. policy retains the old value or writes all ones; tails are not guaranteed zero.

Pre-Use Checklist

Syntax Check
  • Compare vs2[i] with vs1[i] in SEW-wide unsigned order; write the smaller source bits to vd[i]. This sets neither vxsat nor fflags.
  • 32-bit OP-V: opcode=1010111, funct6=000100, funct3=000. [, v0.t] is optional: omitted means vm=1; included means vm=0.
Semantic Check
  • Same-width source/destination overlap is legal; equal sources require equal initial values. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data.
  • Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive elements follow vma; tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.

Pitfalls / Common Confusions

VMINU selects one source element pattern; it is not addition, subtraction, or a saturating operation.
Unsigned forms compare the SEW bit patterns as unsigned integers, so a value with the top bit set is usually larger than one with the top bit clear.
The VV form takes its second source from vector register vs1 and does not read an integer scalar register.
With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.
Body is vstart≤i<vl; prestart is unchanged, inactive elements follow vma, and tails follow vta. vl=0 or vstart≥vl updates no destination, including tails.
Require V 1.0, valid vtype, supported SEW, and enabled VS. A masked vd cannot include v0; v0 cannot supply both EEW=1 mask and SEW data. Same-width source/destination overlap is legal.

FAQ

How does VMINU.VV differ from the signed form?

VMINU.VV uses unsigned integer ordering; the non-U form uses signed integer ordering. Both write back the selected source element's SEW-bit pattern.

Does VMINU.VV set vxsat or fflags?

VMINU.VV compares and selects source bits; it neither sets vxsat or fflags nor clears existing flags. This does not rule out exceptions for invalid vtype, disabled VS, or reserved encodings.

How do vm and v0.t affect VMINU.VV?

With vm=0, only body elements whose v0.t bit is 1 execute the compare; with vm=1, body elements within the current vl are active. Masked-off and tail destination elements follow the current vtype policies.